branch_ctrl.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 40 行

module BRANCH_CTRL(BranchOp, AluZero, Branch);
    input [1:0] BranchOp;
    wire [1:0] BranchOp;
    input [0:0] AluZero;
    wire [0:0] AluZero;
    output [0:0] Branch;
    reg [0:0] Branch;
    reg [1:0] branchop;
    reg [0:0] aluzero;
    reg [0:0] branch;
    reg [0:0] __tmp61;
    reg [0:0] __tmp62;
    
    always @(BranchOp or AluZero)
        begin : branch_ctrl_thread
            branchop = BranchOp;
            aluzero = AluZero;
            case (branchop) //synopsys parallel_case full_case
            0:              branch = 1'b0;
            1:  begin
                if (aluzero == 1'b1)
                    __tmp61 = 1'b1;
                else
                    __tmp61 = 1'b0;
                branch = __tmp61;
            end
            2:  begin
                if (aluzero != 1'b1)
                    __tmp62 = 1'b1;
                else
                    __tmp62 = 1'b0;
                branch = __tmp62;
            end
            3:              branch = 1'b1;
            endcase
            Branch = branch;
        end

endmodule