mmips.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 212 行

module mMIPS(clock, enable, reset, bus_pc, romDO, romADDR, romDI, romEN, romCLK, romWE, romRST, ramDO, ramADDR, ramDI, ramEN, ramCLK, ramWE, ramRST, dev_dout, dev_din, dev_r, dev_w, dev_rdyr, dev_rdyw, dev_wdata, dev_waddr, dev_send_eop, dev_rcv_eop);
    input clock;
    wire clock;
    input enable;
    wire enable;
    input reset;
    wire reset;
    output [31:0] bus_pc;
    output signed  [31:0] romDO;
    input [31:0] romADDR;
    wire [31:0] romADDR;
    input signed  [31:0] romDI;
    wire signed [31:0] romDI;
    input romEN;
    wire romEN;
    input romCLK;
    wire romCLK;
    input romWE;
    wire romWE;
    input romRST;
    wire romRST;
    output signed  [31:0] ramDO;
    input [31:0] ramADDR;
    wire [31:0] ramADDR;
    input signed  [31:0] ramDI;
    wire signed [31:0] ramDI;
    input ramEN;
    wire ramEN;
    input ramCLK;
    wire ramCLK;
    input ramWE;
    wire ramWE;
    input ramRST;
    wire ramRST;
    output [31:0] dev_dout;
    input [31:0] dev_din;
    wire [31:0] dev_din;
    output dev_r;
    output dev_w;
    input dev_rdyr;
    wire dev_rdyr;
    input dev_rdyw;
    wire dev_rdyw;
    output dev_wdata;
    output dev_waddr;
    output dev_send_eop;
    input dev_rcv_eop;
    wire dev_rcv_eop;
    wire clk;
    wire [31:0] bus_mux6;
    wire [31:0] bus_ex_alu_result;
    wire [31:0] bus_dmem_1;
    wire [31:0] bus_id_data_reg2;
    wire [1:0] bus_id_ctrl_mem_memwrite;
    wire [1:0] bus_id_ctrl_mem_memread;
    wire bus_dmem_wait;
    wire [31:0] bus_ram_dout;
    wire bus_ram_wait;
    wire [1:0] bus_ram_w;
    wire [1:0] bus_ram_r;
    wire [31:0] bus_ram_addr;
    wire [31:0] bus_ram_din;
    wire [31:0] bus_alu_result;
    wire [31:0] bus_if_pc;
    wire [0:0] bus_id_ctrl_ex_regvalue;
    wire [31:0] bus_add2;
    wire [31:0] bus_shiftleft_jmp;
    wire [31:0] bus_id_data_reg1;
    wire [1:0] bus_id_ctrl_ex_target;
    wire [31:0] bus_mux5;
    wire [4:0] bus_id_instr_20_16;
    wire [4:0] bus_id_instr_15_11;
    wire [4:0] bus_ctrl_c31;
    wire [1:0] bus_id_ctrl_ex_regdst;
    wire [4:0] bus_mux4;
    wire [31:0] bus_mem_alu_result;
    wire [31:0] bus_mem_dmem_data;
    wire [31:0] bus_signextendbyte;
    wire [1:0] bus_mem_ctrl_wb_memtoreg;
    wire [31:0] bus_mux3;
    wire [31:0] bus_id_immediate;
    wire [0:0] bus_id_ctrl_ex_alusrc;
    wire [31:0] bus_mux2;
    wire [31:0] bus_add1;
    wire [0:0] bus_branch;
    wire [31:0] bus_mux1;
    wire [31:0] bus_mux7;
    wire [4:0] bus_decoder_nb_instr_25_21;
    wire [4:0] bus_decoder_nb_instr_20_16;
    wire [31:0] bus_if_instr;
    wire [31:0] bus_imem_1;
    wire [0:0] bus_hazard_ifidwrite;
    wire [5:0] bus_decoder_instr_31_26;
    wire [31:0] bus_decoder_instr_25_0;
    wire [4:0] bus_decoder_instr_25_21;
    wire [4:0] bus_decoder_instr_20_16;
    wire [4:0] bus_decoder_instr_15_11;
    wire [15:0] bus_decoder_instr_15_0;
    wire [4:0] bus_decoder_instr_10_6;
    wire [5:0] bus_decoder_instr_5_0;
    wire [0:0] bus_ctrl_enable;
    wire [1:0] bus_ctrl2hazard_regdst;
    wire [0:0] bus_ctrl2hazard_regvalue;
    wire [1:0] bus_ctrl2hazard_target;
    wire [1:0] bus_ctrl2hazard_branch;
    wire [1:0] bus_ctrl2hazard_memread;
    wire [1:0] bus_ctrl2hazard_memtoreg;
    wire [4:0] bus_ctrl2hazard_aluop;
    wire [1:0] bus_ctrl2hazard_memwrite;
    wire [0:0] bus_ctrl2hazard_alusrc;
    wire [0:0] bus_ctrl2hazard_regwrite;
    wire [0:0] bus_ctrl_signextend;
    wire [31:0] bus_ctrl_c4;
    wire [0:0] bus_ctrl_c1;
    wire [31:0] bus_id_instr_25_0;
    wire [31:0] bus_shiftleft;
    wire [31:0] bus_imm2word;
    wire [5:0] bus_id_instr_5_0;
    wire [4:0] bus_id_ctrl_ex_aluop;
    wire [4:0] bus_id_instr_10_6;
    wire [5:0] bus_aluctrl;
    wire [0:0] bus_alu_zero;
    wire [31:0] bus_registers_1;
    wire [31:0] bus_registers_2;
    wire [4:0] bus_mem_regdst_addr;
    wire [0:0] bus_mem_ctrl_wb_regwrite;
    wire [0:0] bus_dmem_en;
    wire [0:0] bus_imem_en;
    wire bus_imem_wait;
    wire [31:0] bus_id_pc;
    wire [1:0] bus_id_ctrl_mem_branch;
    wire [0:0] bus_hazard_hazard;
    wire [1:0] bus_ctrl_regdst;
    wire [0:0] bus_ctrl_regvalue;
    wire [1:0] bus_ctrl_target;
    wire [1:0] bus_ctrl_branch;
    wire [1:0] bus_ctrl_memread;
    wire [1:0] bus_ctrl_memtoreg;
    wire [4:0] bus_ctrl_aluop;
    wire [1:0] bus_ctrl_memwrite;
    wire [0:0] bus_ctrl_alusrc;
    wire [0:0] bus_ctrl_regwrite;
    wire [0:0] bus_ex_ctrl_wb_regwrite;
    wire [0:0] bus_id_ctrl_wb_regwrite;
    wire [4:0] bus_ex_regdst_addr;
    wire [0:0] bus_hazard_pcwrite;
    wire [0:0] bus_pipe_en;
    wire [1:0] bus_ex_ctrl_wb_memtoreg;
    wire [1:0] bus_id_ctrl_wb_memtoreg;
    wire [0:0] VCC;
    wire [0:0] GND;
    MEMDEV memdev(.clk(clk), .a_read(bus_mux6), .a_read_reg(bus_ex_alu_result), .d_read(bus_dmem_1), .d_write(bus_id_data_reg2), .w(bus_id_ctrl_mem_memwrite), .r(bus_id_ctrl_mem_memread), .dmem_wait(bus_dmem_wait), .ram_dout(bus_ram_dout), .ram_wait(bus_ram_wait), .ram_w(bus_ram_w), .ram_r(bus_ram_r), .ram_addr(bus_ram_addr), .ram_din(bus_ram_din), .dev_dout(dev_din), .dev_rdyr(dev_rdyr), .dev_rdyw(dev_rdyw), .dev_w(dev_w), .dev_r(dev_r), .dev_din(dev_dout), .dev_wdata(dev_wdata), .dev_waddr(dev_waddr), .dev_rcv_eop(dev_rcv_eop), .dev_send_eop(dev_send_eop));
    CLKDIST clkdist(.clkin(clock), .clkout(clk));
    MUX2 mux6(.in0(bus_alu_result), .in1(bus_if_pc), .sel(bus_id_ctrl_ex_regvalue), .out(bus_mux6));
    MUX3 mux5(.in0(bus_add2), .in1(bus_shiftleft_jmp), .in2(bus_id_data_reg1), .sel(bus_id_ctrl_ex_target), .out(bus_mux5));
    MUX3_AWORDREG mux4(.in0(bus_id_instr_20_16), .in1(bus_id_instr_15_11), .in2(bus_ctrl_c31), .sel(bus_id_ctrl_ex_regdst), .out(bus_mux4));
    MUX3 mux3(.in0(bus_mem_alu_result), .in1(bus_mem_dmem_data), .in2(bus_signextendbyte), .sel(bus_mem_ctrl_wb_memtoreg), .out(bus_mux3));
    MUX2 mux2(.in0(bus_id_data_reg2), .in1(bus_id_immediate), .sel(bus_id_ctrl_ex_alusrc), .out(bus_mux2));
    MUX2 mux1(.in0(bus_add1), .in1(bus_mux5), .sel(bus_branch), .out(bus_mux1));
    DECODER_NBUF decoder_nb(.instr(bus_mux7), .instr_25_21(bus_decoder_nb_instr_25_21), .instr_20_16(bus_decoder_nb_instr_20_16));
    MUX2 mux7(.in0(bus_if_instr), .in1(bus_imem_1), .sel(bus_hazard_ifidwrite), .out(bus_mux7));
    DECODER decoder(.instr(bus_if_instr), .instr_31_26(bus_decoder_instr_31_26), .instr_25_0(bus_decoder_instr_25_0), .instr_25_21(bus_decoder_instr_25_21), .instr_20_16(bus_decoder_instr_20_16), .instr_15_11(bus_decoder_instr_15_11), .instr_15_0(bus_decoder_instr_15_0), .instr_10_6(bus_decoder_instr_10_6), .instr_5_0(bus_decoder_instr_5_0));
    CTRL ctrl(.enable(enable), .en(bus_ctrl_enable), .Opcode(bus_decoder_instr_31_26), .FunctionCode(bus_decoder_instr_5_0), .RegDst(bus_ctrl2hazard_regdst), .RegValue(bus_ctrl2hazard_regvalue), .Target(bus_ctrl2hazard_target), .Branch(bus_ctrl2hazard_branch), .MemRead(bus_ctrl2hazard_memread), .MemtoReg(bus_ctrl2hazard_memtoreg), .ALUop(bus_ctrl2hazard_aluop), .MemWrite(bus_ctrl2hazard_memwrite), .ALUSrc(bus_ctrl2hazard_alusrc), .RegWrite(bus_ctrl2hazard_regwrite), .SignExtend(bus_ctrl_signextend), .c4(bus_ctrl_c4), .c1(bus_ctrl_c1), .c31(bus_ctrl_c31));
    SHIFTLEFT shiftleft_jmp(.in(bus_id_instr_25_0), .out(bus_shiftleft_jmp));
    SHIFTLEFT shiftleft(.in(bus_id_immediate), .out(bus_shiftleft));
    SIGNEXTEND_BYTE signextendbyte(.in(bus_mem_dmem_data), .out(bus_signextendbyte));
    IMM2WORD imm2word(.in(bus_decoder_instr_15_0), .signextend(bus_ctrl_signextend), .out(bus_imm2word));
    ALUCTRL aluctrl(.functionCode(bus_id_instr_5_0), .ALUop(bus_id_ctrl_ex_aluop), .Shamt(bus_id_instr_10_6), .ALUctrl(bus_aluctrl));
    ALU alu(.ctrl(bus_aluctrl), .a(bus_id_data_reg1), .b(bus_mux2), .r(bus_alu_result), .z(bus_alu_zero));
    REGFILE16 registers(.r_addr_reg1(bus_decoder_nb_instr_25_21), .r_data_reg1(bus_registers_1), .r_addr_reg2(bus_decoder_nb_instr_20_16), .r_data_reg2(bus_registers_2), .w_addr_reg(bus_mem_regdst_addr), .w_data_reg(bus_mux3), .w(bus_mem_ctrl_wb_regwrite), .clk(clk));
    BRAM16K dmem(.addr(bus_ram_addr), .dout(bus_ram_dout), .din(bus_ram_din), .w(bus_ram_w), .r(bus_ram_r), .clk(clk), .en(bus_dmem_en), .memwait(bus_ram_wait), .dbgDO(ramDO), .dbgADDR(ramADDR), .dbgDI(ramDI), .dbgEN(ramEN), .dbgCLK(ramCLK), .dbgWE(ramWE), .dbgRST(ramRST));
    BROM16K imem(.addr(bus_mux1), .dout(bus_imem_1), .clk(clk), .en(bus_imem_en), .memwait(bus_imem_wait), .dbgDO(romDO), .dbgADDR(romADDR), .dbgDI(romDI), .dbgEN(romEN), .dbgCLK(romCLK), .dbgWE(romWE), .dbgRST(romRST));
    ADD add2(.a(bus_id_pc), .b(bus_shiftleft), .r(bus_add2));
    ADD add1(.a(bus_pc), .b(bus_ctrl_c4), .r(bus_add1));
    BRANCH_CTRL branch_ctrl(.BranchOp(bus_id_ctrl_mem_branch), .AluZero(bus_alu_zero), .Branch(bus_branch));
    HAZARD_CTRL hazard_ctrl(.Hazard(bus_hazard_hazard), .CtrlRegDst(bus_ctrl2hazard_regdst), .CtrlRegValue(bus_ctrl2hazard_regvalue), .CtrlTarget(bus_ctrl2hazard_target), .CtrlBranch(bus_ctrl2hazard_branch), .CtrlMemRead(bus_ctrl2hazard_memread), .CtrlMemtoReg(bus_ctrl2hazard_memtoreg), .CtrlALUop(bus_ctrl2hazard_aluop), .CtrlMemWrite(bus_ctrl2hazard_memwrite), .CtrlALUSrc(bus_ctrl2hazard_alusrc), .CtrlRegWrite(bus_ctrl2hazard_regwrite), .RegDst(bus_ctrl_regdst), .RegValue(bus_ctrl_regvalue), .Target(bus_ctrl_target), .Branch(bus_ctrl_branch), .MemRead(bus_ctrl_memread), .MemtoReg(bus_ctrl_memtoreg), .ALUop(bus_ctrl_aluop), .MemWrite(bus_ctrl_memwrite), .ALUSrc(bus_ctrl_alusrc), .RegWrite(bus_ctrl_regwrite));
    HAZARD hazard(.enable(bus_ctrl_enable), .MEMWBRegWrite(bus_mem_ctrl_wb_regwrite), .EXMEMRegWrite(bus_ex_ctrl_wb_regwrite), .IDEXRegWrite(bus_id_ctrl_wb_regwrite), .IDEXRegDst(bus_id_ctrl_ex_regdst), .IDEXWriteRegisterRt(bus_id_instr_20_16), .IDEXWriteRegisterRd(bus_id_instr_15_11), .EXMEMWriteRegister(bus_ex_regdst_addr), .MEMWBWriteRegister(bus_mem_regdst_addr), .Instr(bus_if_instr), .BranchOp(bus_id_ctrl_mem_branch), .dmem_wait(bus_dmem_wait), .imem_wait(bus_imem_wait), .PCWrite(bus_hazard_pcwrite), .IFIDWrite(bus_hazard_ifidwrite), .Hazard(bus_hazard_hazard), .pipe_en(bus_pipe_en), .dmem_en(bus_dmem_en), .imem_en(bus_imem_en));
    REGISTER_DWORD pc(.in(bus_mux1), .w(bus_hazard_pcwrite), .out(bus_pc), .rst(reset), .clk(clk));
    REGISTER_W_MEMTOREG mem_ctrl_wb_memtoreg(.in(bus_ex_ctrl_wb_memtoreg), .w(bus_pipe_en), .out(bus_mem_ctrl_wb_memtoreg), .rst(reset), .clk(clk));
    REGISTER_W_REGWRITE mem_ctrl_wb_regwrite(.in(bus_ex_ctrl_wb_regwrite), .w(bus_pipe_en), .out(bus_mem_ctrl_wb_regwrite), .rst(reset), .clk(clk));
    REGISTER_AWORDREG mem_regdst_addr(.in(bus_ex_regdst_addr), .w(bus_pipe_en), .out(bus_mem_regdst_addr), .rst(reset), .clk(clk));
    REGISTER_DWORD mem_alu_result(.in(bus_ex_alu_result), .w(bus_pipe_en), .out(bus_mem_alu_result), .rst(reset), .clk(clk));
    REGISTER_DWORD mem_dmem_data(.in(bus_dmem_1), .w(bus_pipe_en), .out(bus_mem_dmem_data), .rst(reset), .clk(clk));
    REGISTER_W_MEMTOREG ex_ctrl_wb_memtoreg(.in(bus_id_ctrl_wb_memtoreg), .w(bus_pipe_en), .out(bus_ex_ctrl_wb_memtoreg), .rst(reset), .clk(clk));
    REGISTER_W_REGWRITE ex_ctrl_wb_regwrite(.in(bus_id_ctrl_wb_regwrite), .w(bus_pipe_en), .out(bus_ex_ctrl_wb_regwrite), .rst(reset), .clk(clk));
    REGISTER_DWORD ex_alu_result(.in(bus_mux6), .w(bus_pipe_en), .out(bus_ex_alu_result), .rst(reset), .clk(clk));
    REGISTER_AWORDREG ex_regdst_addr(.in(bus_mux4), .w(bus_pipe_en), .out(bus_ex_regdst_addr), .rst(reset), .clk(clk));
    REGISTER_W_MEMTOREG id_ctrl_wb_memtoreg(.in(bus_ctrl_memtoreg), .w(bus_pipe_en), .out(bus_id_ctrl_wb_memtoreg), .rst(reset), .clk(clk));
    REGISTER_W_REGWRITE id_ctrl_wb_regwrite(.in(bus_ctrl_regwrite), .w(bus_pipe_en), .out(bus_id_ctrl_wb_regwrite), .rst(reset), .clk(clk));
    REGISTER_W_MEMREAD id_ctrl_mem_memread(.in(bus_ctrl_memread), .w(bus_pipe_en), .out(bus_id_ctrl_mem_memread), .rst(reset), .clk(clk));
    REGISTER_W_MEMWRITE id_ctrl_mem_memwrite(.in(bus_ctrl_memwrite), .w(bus_pipe_en), .out(bus_id_ctrl_mem_memwrite), .rst(reset), .clk(clk));
    REGISTER_W_BRANCHOP id_ctrl_mem_branch(.in(bus_ctrl_branch), .w(bus_pipe_en), .out(bus_id_ctrl_mem_branch), .rst(reset), .clk(clk));
    REGISTER_W_TARGET id_ctrl_ex_target(.in(bus_ctrl_target), .w(bus_pipe_en), .out(bus_id_ctrl_ex_target), .rst(reset), .clk(clk));
    REGISTER_W_REGVAL id_ctrl_ex_regvalue(.in(bus_ctrl_regvalue), .w(bus_pipe_en), .out(bus_id_ctrl_ex_regvalue), .rst(reset), .clk(clk));
    REGISTER_W_REGDST id_ctrl_ex_regdst(.in(bus_ctrl_regdst), .w(bus_pipe_en), .out(bus_id_ctrl_ex_regdst), .rst(reset), .clk(clk));
    REGISTER_W_ALUOP id_ctrl_ex_aluop(.in(bus_ctrl_aluop), .w(bus_pipe_en), .out(bus_id_ctrl_ex_aluop), .rst(reset), .clk(clk));
    REGISTER_W_ALUSRC id_ctrl_ex_alusrc(.in(bus_ctrl_alusrc), .w(bus_pipe_en), .out(bus_id_ctrl_ex_alusrc), .rst(reset), .clk(clk));
    REGISTER_5 id_instr_10_6(.in(bus_decoder_instr_10_6), .w(bus_pipe_en), .out(bus_id_instr_10_6), .rst(reset), .clk(clk));
    REGISTER_6 id_instr_5_0(.in(bus_decoder_instr_5_0), .w(bus_pipe_en), .out(bus_id_instr_5_0), .rst(reset), .clk(clk));
    REGISTER_AWORDREG id_instr_15_11(.in(bus_decoder_instr_15_11), .w(bus_pipe_en), .out(bus_id_instr_15_11), .rst(reset), .clk(clk));
    REGISTER_AWORDREG id_instr_20_16(.in(bus_decoder_instr_20_16), .w(bus_pipe_en), .out(bus_id_instr_20_16), .rst(reset), .clk(clk));
    REGISTER_DWORD id_instr_25_0(.in(bus_decoder_instr_25_0), .w(bus_pipe_en), .out(bus_id_instr_25_0), .rst(reset), .clk(clk));
    REGISTER_DWORD id_immediate(.in(bus_imm2word), .w(bus_pipe_en), .out(bus_id_immediate), .rst(reset), .clk(clk));
    REGISTER_DWORD id_data_reg2(.in(bus_registers_2), .w(bus_pipe_en), .out(bus_id_data_reg2), .rst(reset), .clk(clk));
    REGISTER_DWORD id_data_reg1(.in(bus_registers_1), .w(bus_pipe_en), .out(bus_id_data_reg1), .rst(reset), .clk(clk));
    REGISTER_DWORD id_pc(.in(bus_if_pc), .w(bus_pipe_en), .out(bus_id_pc), .rst(reset), .clk(clk));
    REGISTER_DWORD if_instr(.in(bus_imem_1), .w(bus_hazard_ifidwrite), .out(bus_if_instr), .rst(reset), .clk(clk));
    REGISTER_DWORD if_pc(.in(bus_add1), .w(bus_hazard_ifidwrite), .out(bus_if_pc), .rst(reset), .clk(clk));
    assign VCC = 1'b1;
    assign GND = 1'b0;
endmodule