cache_mainmem_arbiter.v

基于4个mips核的noc设计

module CACHE_MAINMEM_ARBITER(clk, addr0, addr1, din0, din1, dout, ww0, ww1, wb0, wb1, r0, r1, rdy0, rdy1, mem_addr, mem_dout, mem_din, mem_wb, mem_ww, mem_r, mem_clk);
    input clk;
    wire clk;
    input [31:0] addr0;
    wire [31:0] addr0;
    input [31:0] addr1;
    wire [31:0] addr1;
    input [31:0] din0;
    wire [31:0] din0;
    input [31:0] din1;
    wire [31:0] din1;
    output [31:0] dout;
    reg [31:0] dout;
    input ww0;
    wire ww0;
    input ww1;
    wire ww1;
    input wb0;
    wire wb0;
    input wb1;
    wire wb1;
    input r0;
    wire r0;
    input r1;
    wire r1;
    output rdy0;
    reg rdy0;
    output rdy1;
    reg rdy1;
    output [31:0] mem_addr;
    reg [31:0] mem_addr;
    input signed  [31:0] mem_dout;
    wire signed [31:0] mem_dout;
    output signed  [31:0] mem_din;
    reg signed [31:0] mem_din;
    output mem_wb;
    reg mem_wb;
    output mem_ww;
    reg mem_ww;
    output mem_r;
    reg mem_r;
    output mem_clk;
    reg mem_clk;
    reg req0;
    reg req1;
    reg req0_reg;
    reg ww0_reg;
    reg wb0_reg;
    reg r0_reg;
    reg req1_reg;
    reg ww1_reg;
    reg wb1_reg;
    reg r1_reg;
    reg reg0_v;
    reg reg1_v;
    reg clr0_v;
    reg clr1_v;
    reg wb;
    reg ww;
    reg r;
    reg [31:0] mem_din_v;
    reg [31:0] din0_reg;
    reg [13:0] a_tail;
    reg [31:0] addr0_reg;
    reg [14:0] address;
    reg [1:0] n_grant;
    reg [31:0] addr1_reg;
    reg [31:0] din1_reg;
    reg reg0;
    reg reg1;
    reg clr0;
    reg clr1;
    reg [1:0] grant;
    
    always @(grant or clk or addr0 or addr1 or din0 or din1 or ww0 or ww1 or wb0 or wb1 or r0 or r1 or addr0_reg or addr1_reg or din0_reg or din1_reg or ww0_reg or ww1_reg or wb0_reg or wb1_reg or r0_reg or r1_reg)
        begin : select
            req0 = ww0 || wb0 || r0;
            req1 = ww1 || wb1 || r1;
            req0_reg = ww0_reg || wb0_reg || r0_reg;
            req1_reg = ww1_reg || wb1_reg || r1_reg;
            reg0_v = 0;
            reg1_v = 0;
            clr0_v = 0;
            clr1_v = 0;
            wb = 0;
            ww = 0;
            r = 0;
            mem_din_v = din0_reg;
            a_tail = addr0_reg[13:0];
            address = a_tail | 14'b00000000000000;
            n_grant = 2'b00;
            if (req0_reg)
            begin
                wb = wb0_reg;
                ww = ww0_reg;
                r = r0_reg;
                a_tail = addr0_reg[13:0];
                address = a_tail | 14'b00000000000000;
                mem_din_v = din0_reg;
                n_grant = 2'b01;
                if (req0)
                    reg0_v = 1;
                else
                    clr0_v = 1;
                if (req1)
                    reg1_v = 1;
            end
            else
            begin
                if (req1_reg)
                begin
                    wb = wb1_reg;
                    ww = ww1_reg;
                    r = r1_reg;
                    a_tail = addr1_reg[13:0];
                    address = a_tail | 15'b100000000000000;
                    mem_din_v = din1_reg;
                    n_grant = 2'b10;
                    if (req0)
                        reg0_v = 1;
                    if (req1)
                        reg1_v = 1;
                    else
                        clr1_v = 1;
                end
                else
                begin
                    if (req0)
                    begin
                        wb = wb0;
                        ww = ww0;
                        r = r0;
                        a_tail = addr0[13:0];
                        address = a_tail | 14'b00000000000000;
                        mem_din_v = din0;
                        n_grant = 2'b01;
                        if (req1)
                            reg1_v = 1;
                    end
                    else
                    begin
                        if (req1)
                        begin
                            wb = wb1;
                            ww = ww1;
                            r = r1;
                            a_tail = addr1[13:0];
                            address = a_tail | 15'b100000000000000;
                            mem_din_v = din1;
                            n_grant = 2'b10;
                            if (req0)
                                reg0_v = 1;
                        end
                    end
                end
            end
            reg0 = reg0_v;
            reg1 = reg1_v;
            clr0 = clr0_v;
            clr1 = clr1_v;
            mem_addr = {17'b00000000000000000, address};
            mem_r = r;
            mem_ww = ww;
            mem_wb = wb;
            mem_clk = clk;
            mem_din = mem_din_v;
            rdy0 = grant[1'b0] == 1;
            rdy1 = grant[1'b1] == 1;
        end

    
    always @(mem_dout)
        begin : output__17
            dout = mem_dout;
        end

    
    always @(posedge clk)
        begin : reg__18
            if (reg0)
            begin
                addr0_reg <= addr0;
                din0_reg <= din0;
                ww0_reg <= ww0;
                wb0_reg <= wb0;
                r0_reg <= r0;
            end
            else
            begin
                if (clr0)
                begin
                    addr0_reg <= 32'b00000000000000000000000000000000;
                    din0_reg <= 32'b00000000000000000000000000000000;
                    ww0_reg <= 0;
                    wb0_reg <= 0;
                    r0_reg <= 0;
                end
            end
            if (reg1)
            begin
                addr1_reg <= addr1;
                din1_reg <= din1;
                ww1_reg <= ww1;
                wb1_reg <= wb1;
                r1_reg <= r1;
            end
            else
            begin
                if (clr1)
                begin
                    addr1_reg <= 32'b00000000000000000000000000000000;
                    din1_reg <= 32'b00000000000000000000000000000000;
                    ww1_reg <= 0;
                    wb1_reg <= 0;
                    r1_reg <= 0;
                end
            end
            grant <= n_grant;
        end

endmodule