cache_byte_select.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 35 行

module CACHE_BYTE_SELECT(din, r, byte, dout);
    input [31:0] din;
    wire [31:0] din;
    input [1:0] r;
    wire [1:0] r;
    input [1:0] byte;
    wire [1:0] byte;
    output [31:0] dout;
    reg [31:0] dout;
    reg [31:0] data;
    reg [23:0] lsbs;
    reg [1:0] r_v;
    reg [7:0] msb;
    
    always @(din or byte or r)
        begin : select
            data = din;
            lsbs = data[23:0];
            r_v = r;
            if (r_v == 2'b10)
                case (byte) //synopsys parallel_case
                1:                  msb = data[23:16];
                2:                  msb = data[15:8];
                3:                  msb = data[7:0];
                default : begin 
                    msb = data[31:24];
                    end
                endcase
            else
                msb = data[31:24];
            dout = {msb, lsbs};
        end

endmodule