signextend.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 24 行

module SIGNEXTEND(in, out);
    input [15:0] in;
    wire [15:0] in;
    output [31:0] out;
    reg [31:0] out;
    reg [15:0] zero;
    reg [15:0] a;
    reg [31:0] b;
    reg [5:0] i__loop_37;
    reg [31:0] i;
    
    always @(in)
        begin : signextend_thread
            zero = 16'b0000000000000000;
            a = in;
            b = {zero, a};
            for (i__loop_37 = 6'b010000 ; i__loop_37 < 6'b100000 ; i__loop_37 = 6'b000001 + i__loop_37)
                        b[i__loop_37] = a[4'b1111];
            i = i__loop_37;
            out = b;
        end

endmodule