cache_din_select.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 64 行

module CACHE_DIN_SELECT(din_data, din_data_reg, din_fetch, din_out, rewrite, rewrite_valid, byte_rpl, w, byte, fetch_word_rdy, valid, data);
    input [31:0] din_data;
    wire [31:0] din_data;
    input [31:0] din_data_reg;
    wire [31:0] din_data_reg;
    input [31:0] din_fetch;
    wire [31:0] din_fetch;
    input [31:0] din_out;
    wire [31:0] din_out;
    input rewrite;
    wire rewrite;
    input rewrite_valid;
    wire rewrite_valid;
    input byte_rpl;
    wire byte_rpl;
    input [1:0] w;
    wire [1:0] w;
    input [1:0] byte;
    wire [1:0] byte;
    input fetch_word_rdy;
    wire fetch_word_rdy;
    output valid;
    reg valid;
    output [31:0] data;
    reg [31:0] data;
    reg v;
    reg [31:0] d;
    
    always @(din_data or din_data_reg or din_fetch or din_out or w or byte or fetch_word_rdy or rewrite or rewrite_valid or byte_rpl)
        begin : select
            v = 0;
            if (rewrite)
            begin
                d = din_out;
                if (byte_rpl)
                    case (byte) //synopsys parallel_case
                    0:                      d[31:24] = din_data_reg[7:0];
                    1:                      d[23:16] = din_data_reg[7:0];
                    2:                      d[15:8] = din_data_reg[7:0];
                    default : begin 
                        d[7:0] = din_data_reg[7:0];
                        end
                    endcase
                v = rewrite_valid;
            end
            else
            begin
                if (fetch_word_rdy)
                begin
                    d = din_fetch;
                    v = 1;
                end
                else
                begin
                    d = din_data;
                    v = 1;
                end
            end
            data = d;
            valid = v;
        end

endmodule