arbiter_select_channel.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 67 行

module ARBITER_SELECT_CHANNEL(clk, req0, req1, grant0, grant1, data0, data1, dataout);
    input clk;
    wire clk;
    input req0;
    wire req0;
    input req1;
    wire req1;
    output grant0;
    reg grant0;
    output grant1;
    reg grant1;
    input [17:0] data0;
    wire [17:0] data0;
    input [17:0] data1;
    wire [17:0] data1;
    output [17:0] dataout;
    reg [17:0] dataout;
    reg r0;
    reg r1;
    reg ch_bsy;
    reg channel_busy;
    reg selected_channel;
    reg [17:0] __tmp63;
    
    always @(posedge clk)
        begin : select
            r0 = req0;
            r1 = req1;
            ch_bsy = channel_busy;
            if (ch_bsy)
            begin
                if (selected_channel && !r1 || !selected_channel && !r0)
                    ch_bsy = 0;
            end
            if (!ch_bsy)
            begin
                if (r0)
                begin
                    selected_channel <= 0;
                    ch_bsy = 1;
                end
                else
                begin
                    if (r1)
                    begin
                        selected_channel <= 1;
                        ch_bsy = 1;
                    end
                end
            end
            channel_busy <= ch_bsy;
        end

    
    always @(req0 or req1 or data0 or data1 or channel_busy or selected_channel)
        begin : output__17
            if (selected_channel)
                __tmp63 = data1;
            else
                __tmp63 = data0;
            dataout = __tmp63;
            grant0 = channel_busy && !selected_channel;
            grant1 = channel_busy && selected_channel;
        end

endmodule