output_queue.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 91 行

module OUTPUT_QUEUE(clk, rst, ack, req, data, req_in, ack_in, data_in);
    input clk;
    wire clk;
    input rst;
    wire rst;
    input ack;
    wire ack;
    output req;
    reg req;
    output [17:0] data;
    reg [17:0] data;
    input req_in;
    wire req_in;
    output ack_in;
    reg ack_in;
    input [17:0] data_in;
    wire [17:0] data_in;
    reg req_v;
    reg ack_in_v;
    reg buffer_write_v;
    reg buffer_clear_v;
    reg [0:0] next_state;
    reg [0:0] current_state;
    reg buffer_write;
    reg buffer_clear;
    reg [17:0] buffer;
    
    always @(current_state or req_in or ack)
        begin : control_logic
            req_v = 0;
            ack_in_v = 0;
            buffer_write_v = 0;
            buffer_clear_v = 0;
            next_state = 1'b0;
            case (current_state) //synopsys parallel_case full_case
            0:              if (req_in)
            begin
                buffer_write_v = 1;
                next_state = 1'b1;
                ack_in_v = 1;
            end
            else
                next_state = 1'b0;
            1:  begin
                req_v = 1;
                if (ack)
                    next_state = 1'b0;
                else
                    next_state = 1'b1;
            end
            endcase
            req = req_v;
            ack_in = ack_in_v;
            buffer_write = buffer_write_v;
            buffer_clear = buffer_clear_v;
        end

    
    always @(posedge clk or posedge rst)
        begin : control_change_state
            if (rst)
                current_state <= 1'b0;
            else
                current_state <= next_state;
        end

    
    always @(posedge clk)
        begin : buffer_process
            if (rst)
                buffer <= 18'b000000000000000000;
            else
            begin
                if (buffer_clear)
                    buffer <= 18'b000000000000000000;
                else
                begin
                    if (buffer_write)
                        buffer <= data_in;
                end
            end
        end

    
    always @(buffer)
        begin : data_out
            data = buffer;
        end

endmodule