imm2word.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 29 行

module IMM2WORD(in, signextend, out);
    input [15:0] in;
    wire [15:0] in;
    input [0:0] signextend;
    wire [0:0] signextend;
    output [31:0] out;
    reg [31:0] out;
    reg [15:0] zero;
    reg [15:0] a;
    reg [31:0] b;
    reg [5:0] i__loop_40;
    reg [31:0] i;
    
    always @(in or signextend)
        begin : imm2word_thread
            zero = 16'b0000000000000000;
            a = in;
            b = {zero, a};
            if (signextend == 1'b1)
            begin
                for (i__loop_40 = 6'b010000 ; i__loop_40 < 6'b100000 ; i__loop_40 = 6'b000001 + i__loop_40)
                                b[i__loop_40] = a[4'b1111];
                i = i__loop_40;
            end
            out = b;
        end

endmodule