xramconv.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 53 行

module XRAMCONV(DO, ADDR, DI, CLK, addr_cnt, DO0, DO1, DO2, DO3, DI0, DI1, DI2, DI3, wADDR, rADDR, wCLK);
    output signed  [31:0] DO;
    reg signed [31:0] DO;
    input [31:0] ADDR;
    wire [31:0] ADDR;
    input signed  [31:0] DI;
    wire signed [31:0] DI;
    input CLK;
    wire CLK;
    input [10:0] addr_cnt;
    wire [10:0] addr_cnt;
    input signed  [7:0] DO0;
    wire signed [7:0] DO0;
    input signed  [7:0] DO1;
    wire signed [7:0] DO1;
    input signed  [7:0] DO2;
    wire signed [7:0] DO2;
    input signed  [7:0] DO3;
    wire signed [7:0] DO3;
    output signed  [7:0] DI0;
    reg signed [7:0] DI0;
    output signed  [7:0] DI1;
    reg signed [7:0] DI1;
    output signed  [7:0] DI2;
    reg signed [7:0] DI2;
    output signed  [7:0] DI3;
    reg signed [7:0] DI3;
    output [10:0] wADDR;
    reg [10:0] wADDR;
    output [10:0] rADDR;
    reg [10:0] rADDR;
    output wCLK;
    reg wCLK;
    
    always @(ADDR or DI or addr_cnt or CLK)
        begin : in
            wADDR = {21'b000000000000000000000, addr_cnt};
            rADDR = ADDR;
            DI3 = DI[7:0];
            DI2 = DI[15:8];
            DI1 = DI[23:16];
            DI0 = DI[31:24];
            wCLK = !CLK;
        end

    
    always @(DO0 or DO1 or DO2 or DO3)
        begin : out
            DO = {DO0, DO1, DO2, DO3};
        end

endmodule