register_w_regwrite.v

基于4个mips核的noc设计

module REGISTER_W_REGWRITE(in, w, out, rst, clk);
    input [0:0] in;
    wire [0:0] in;
    input [0:0] w;
    wire [0:0] w;
    output [0:0] out;
    reg [0:0] out;
    input rst;
    wire rst;
    input clk;
    wire clk;
    
    always @(posedge clk or posedge rst)
        begin : reg_thread
            if (rst == 1)
                out <= 1'b0;
            else
            begin
                if (w[1'b0] == 1)
                    out <= in;
            end
        end

endmodule