bram16k.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 85 行

module BRAM16K(addr, dout, din, w, r, clk, en, memwait, dbgDO, dbgADDR, dbgDI, dbgEN, dbgCLK, dbgWE, dbgRST);
    input [31:0] addr;
    wire [31:0] addr;
    output [31:0] dout;
    input [31:0] din;
    wire [31:0] din;
    input [1:0] w;
    wire [1:0] w;
    input [1:0] r;
    wire [1:0] r;
    input clk;
    wire clk;
    input [0:0] en;
    wire [0:0] en;
    output memwait;
    output signed  [31:0] dbgDO;
    input [31:0] dbgADDR;
    wire [31:0] dbgADDR;
    input signed  [31:0] dbgDI;
    wire signed [31:0] dbgDI;
    input dbgEN;
    wire dbgEN;
    input dbgCLK;
    wire dbgCLK;
    input dbgWE;
    wire dbgWE;
    input dbgRST;
    wire dbgRST;
    wire [11:0] dADDR;
    wire signed [3:0] dDI00;
    wire signed [3:0] dDI01;
    wire signed [3:0] dDI02;
    wire signed [3:0] dDI03;
    wire signed [3:0] dDI04;
    wire signed [3:0] dDI05;
    wire signed [3:0] dDI06;
    wire signed [3:0] dDI07;
    wire dEN;
    wire dCLK;
    wire dSSR;
    wire dWE;
    wire signed [3:0] dDO00;
    wire signed [3:0] dDO01;
    wire signed [3:0] dDO02;
    wire signed [3:0] dDO03;
    wire signed [3:0] dDO04;
    wire signed [3:0] dDO05;
    wire signed [3:0] dDO06;
    wire signed [3:0] dDO07;
    wire [11:0] ADDR;
    wire signed [3:0] DI00;
    wire signed [3:0] DI01;
    wire signed [3:0] DI02;
    wire signed [3:0] DI03;
    wire signed [3:0] DI04;
    wire signed [3:0] DI05;
    wire signed [3:0] DI06;
    wire signed [3:0] DI07;
    wire EN;
    wire CLK;
    wire SSR;
    wire WE0;
    wire WE1;
    wire WE2;
    wire WE3;
    wire signed [3:0] DO00;
    wire signed [3:0] DO01;
    wire signed [3:0] DO02;
    wire signed [3:0] DO03;
    wire signed [3:0] DO04;
    wire signed [3:0] DO05;
    wire signed [3:0] DO06;
    wire signed [3:0] DO07;
    BRAM16K_DBGWRAPPER dbgconv(.DO(dbgDO), .ADDR(dbgADDR), .DI(dbgDI), .EN(dbgEN), .CLK(dbgCLK), .WE(dbgWE), .RST(dbgRST), .dADDR(dADDR), .dDI00(dDI00), .dDI01(dDI01), .dDI02(dDI02), .dDI03(dDI03), .dDI04(dDI04), .dDI05(dDI05), .dDI06(dDI06), .dDI07(dDI07), .dEN(dEN), .dCLK(dCLK), .dSSR(dSSR), .dWE(dWE), .dDO00(dDO00), .dDO01(dDO01), .dDO02(dDO02), .dDO03(dDO03), .dDO04(dDO04), .dDO05(dDO05), .dDO06(dDO06), .dDO07(dDO07));
    BRAM16K_WRAPPER conv(.addr(addr), .dout(dout), .din(din), .w(w), .r(r), .clk(clk), .en(en), .memwait(memwait), .ADDR(ADDR), .DI00(DI00), .DI01(DI01), .DI02(DI02), .DI03(DI03), .DI04(DI04), .DI05(DI05), .DI06(DI06), .DI07(DI07), .EN(EN), .CLK(CLK), .SSR(SSR), .WE0(WE0), .WE1(WE1), .WE2(WE2), .WE3(WE3), .DO00(DO00), .DO01(DO01), .DO02(DO02), .DO03(DO03), .DO04(DO04), .DO05(DO05), .DO06(DO06), .DO07(DO07));
    RAMB16_S4_S4 bram07(.DOA(DO07), .ADDRA(ADDR), .DIA(DI07), .ENA(EN), .CLKA(CLK), .WEA(WE3), .SSRA(SSR), .DOB(dDO07), .ADDRB(dADDR), .DIB(dDI07), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S4_S4 bram06(.DOA(DO06), .ADDRA(ADDR), .DIA(DI06), .ENA(EN), .CLKA(CLK), .WEA(WE3), .SSRA(SSR), .DOB(dDO06), .ADDRB(dADDR), .DIB(dDI06), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S4_S4 bram05(.DOA(DO05), .ADDRA(ADDR), .DIA(DI05), .ENA(EN), .CLKA(CLK), .WEA(WE2), .SSRA(SSR), .DOB(dDO05), .ADDRB(dADDR), .DIB(dDI05), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S4_S4 bram04(.DOA(DO04), .ADDRA(ADDR), .DIA(DI04), .ENA(EN), .CLKA(CLK), .WEA(WE2), .SSRA(SSR), .DOB(dDO04), .ADDRB(dADDR), .DIB(dDI04), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S4_S4 bram03(.DOA(DO03), .ADDRA(ADDR), .DIA(DI03), .ENA(EN), .CLKA(CLK), .WEA(WE1), .SSRA(SSR), .DOB(dDO03), .ADDRB(dADDR), .DIB(dDI03), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S4_S4 bram02(.DOA(DO02), .ADDRA(ADDR), .DIA(DI02), .ENA(EN), .CLKA(CLK), .WEA(WE1), .SSRA(SSR), .DOB(dDO02), .ADDRB(dADDR), .DIB(dDI02), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S4_S4 bram01(.DOA(DO01), .ADDRA(ADDR), .DIA(DI01), .ENA(EN), .CLKA(CLK), .WEA(WE0), .SSRA(SSR), .DOB(dDO01), .ADDRB(dADDR), .DIB(dDI01), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S4_S4 bram00(.DOA(DO00), .ADDRA(ADDR), .DIA(DI00), .ENA(EN), .CLKA(CLK), .WEA(WE0), .SSRA(SSR), .DOB(dDO00), .ADDRB(dADDR), .DIB(dDI00), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
endmodule