hazard.v

基于4个mips核的noc设计

module HAZARD(enable, MEMWBRegWrite, EXMEMRegWrite, IDEXRegWrite, IDEXRegDst, IDEXWriteRegisterRt, IDEXWriteRegisterRd, EXMEMWriteRegister, MEMWBWriteRegister, Instr, BranchOp, dmem_wait, imem_wait, PCWrite, IFIDWrite, Hazard, pipe_en, dmem_en, imem_en);
    input [0:0] enable;
    wire [0:0] enable;
    input [0:0] MEMWBRegWrite;
    wire [0:0] MEMWBRegWrite;
    input [0:0] EXMEMRegWrite;
    wire [0:0] EXMEMRegWrite;
    input [0:0] IDEXRegWrite;
    wire [0:0] IDEXRegWrite;
    input [1:0] IDEXRegDst;
    wire [1:0] IDEXRegDst;
    input [4:0] IDEXWriteRegisterRt;
    wire [4:0] IDEXWriteRegisterRt;
    input [4:0] IDEXWriteRegisterRd;
    wire [4:0] IDEXWriteRegisterRd;
    input [4:0] EXMEMWriteRegister;
    wire [4:0] EXMEMWriteRegister;
    input [4:0] MEMWBWriteRegister;
    wire [4:0] MEMWBWriteRegister;
    input [31:0] Instr;
    wire [31:0] Instr;
    input [1:0] BranchOp;
    wire [1:0] BranchOp;
    input dmem_wait;
    wire dmem_wait;
    input imem_wait;
    wire imem_wait;
    output [0:0] PCWrite;
    reg [0:0] PCWrite;
    output [0:0] IFIDWrite;
    reg [0:0] IFIDWrite;
    output [0:0] Hazard;
    reg [0:0] Hazard;
    output [0:0] pipe_en;
    reg [0:0] pipe_en;
    output [0:0] dmem_en;
    reg [0:0] dmem_en;
    output [0:0] imem_en;
    reg [0:0] imem_en;
    reg [0:0] memwbregwrite_t;
    reg [0:0] exmemregwrite_t;
    reg [0:0] idexregwrite_t;
    reg [1:0] idexregdst_t;
    reg [4:0] idexwriteregisterrt_t;
    reg [4:0] idexwriteregisterrd_t;
    reg [4:0] exmemwriteregister_t;
    reg [4:0] memwbwriteregister_t;
    reg [31:0] instr_t;
    reg [1:0] branchop;
    reg [4:0] ifidreadregister1_t;
    reg [4:0] ifidreadregister2_t;
    reg [0:0] hazard;
    reg [0:0] __tmp62;
    reg [0:0] __tmp63;
    
    always @(MEMWBRegWrite or EXMEMRegWrite or IDEXRegWrite or IDEXRegDst or IDEXWriteRegisterRt or IDEXWriteRegisterRd or BranchOp or EXMEMWriteRegister or MEMWBWriteRegister or Instr or enable or dmem_wait or imem_wait)
        begin : hazard_thread
            memwbregwrite_t = MEMWBRegWrite;
            exmemregwrite_t = EXMEMRegWrite;
            idexregwrite_t = IDEXRegWrite;
            idexregdst_t = IDEXRegDst;
            idexwriteregisterrt_t = IDEXWriteRegisterRt;
            idexwriteregisterrd_t = IDEXWriteRegisterRd;
            exmemwriteregister_t = EXMEMWriteRegister;
            memwbwriteregister_t = MEMWBWriteRegister;
            instr_t = Instr;
            branchop = BranchOp;
            ifidreadregister1_t = instr_t[25:21];
            ifidreadregister2_t = instr_t[20:16];
            imem_en = 1'b1;
            dmem_en = 1'b1;
            pipe_en = 1'b1;
            if (branchop != 2'b00)
                hazard = 1'b1;
            else
            begin
                if (idexregwrite_t == 1'b1 && (idexregdst_t == 2'b00 && idexwriteregisterrt_t == ifidreadregister1_t || idexregdst_t == 2'b01 && idexwriteregisterrd_t == ifidreadregister1_t || idexregdst_t == 2'b00 && idexwriteregisterrt_t == ifidreadregister2_t || idexregdst_t == 2'b01 && idexwriteregisterrd_t == ifidreadregister2_t))
                    hazard = 1'b1;
                else
                begin
                    if (exmemregwrite_t == 1'b1 && (exmemwriteregister_t == ifidreadregister1_t || exmemwriteregister_t == ifidreadregister2_t))
                        hazard = 1'b1;
                    else
                    begin
                        if (memwbregwrite_t == 1'b1 && (memwbwriteregister_t == ifidreadregister1_t || memwbwriteregister_t == ifidreadregister2_t))
                            hazard = 1'b1;
                        else
                            hazard = 1'b0;
                    end
                end
            end
            if (enable[1'b0] == 0)
            begin
                PCWrite = 1'b0;
                IFIDWrite = 1'b0;
                Hazard = hazard;
                imem_en = 1'b0;
                dmem_en = 1'b0;
                pipe_en = 1'b0;
            end
            else
            begin
                if (dmem_wait || imem_wait)
                begin
                    PCWrite = 1'b0;
                    IFIDWrite = 1'b0;
                    Hazard = hazard;
                    if (dmem_wait)
                        imem_en = 1'b0;
                    if (imem_wait)
                        dmem_en = 1'b0;
                    pipe_en = 1'b0;
                end
                else
                begin
                    if (hazard)
                    begin
                        if (branchop)
                            __tmp62 = 1'b1;
                        else
                            __tmp62 = 1'b0;
                        PCWrite = __tmp62;
                        if (branchop)
                            __tmp63 = 1'b1;
                        else
                            __tmp63 = 1'b0;
                        imem_en = __tmp63;
                        IFIDWrite = 1'b0;
                        Hazard = 1'b1;
                    end
                    else
                    begin
                        if (instr_t[31:26] == 6'b000100 || instr_t[31:26] == 6'b000101)
                        begin
                            PCWrite = 1'b0;
                            imem_en = 1'b0;
                        end
                        else
                        begin
                            PCWrite = 1'b1;
                            imem_en = 1'b1;
                        end
                        IFIDWrite = 1'b1;
                        Hazard = 1'b0;
                    end
                end
            end
        end

endmodule