cache_addr_split.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 68 行

module CACHE_ADDR_SPLIT(addr, addr_reg, fetch_word, fetch_word_rdy, tag_rewrite, rewrite, tag, tag_reg, index, index_reg, offset, offset_reg, byte, byte_reg);
    input [31:0] addr;
    wire [31:0] addr;
    input [31:0] addr_reg;
    wire [31:0] addr_reg;
    input [1:0] fetch_word;
    wire [1:0] fetch_word;
    input fetch_word_rdy;
    wire fetch_word_rdy;
    input [19:0] tag_rewrite;
    wire [19:0] tag_rewrite;
    input rewrite;
    wire rewrite;
    output [19:0] tag;
    reg [19:0] tag;
    output [19:0] tag_reg;
    reg [19:0] tag_reg;
    output [7:0] index;
    reg [7:0] index;
    output [7:0] index_reg;
    reg [7:0] index_reg;
    output [1:0] offset;
    reg [1:0] offset;
    output [1:0] offset_reg;
    reg [1:0] offset_reg;
    output [1:0] byte;
    reg [1:0] byte;
    output [1:0] byte_reg;
    reg [1:0] byte_reg;
    reg [31:0] a;
    reg [31:0] ar;
    reg [1:0] b;
    reg [1:0] br;
    reg [1:0] o;
    reg [1:0] ofr;
    reg [7:0] i;
    reg [7:0] ir;
    reg [19:0] t;
    reg [19:0] tr;
    
    always @(addr or addr_reg or fetch_word or fetch_word_rdy or rewrite or tag_rewrite)
        begin : split
            a = addr;
            ar = addr_reg;
            b = a[1:0];
            br = ar[1:0];
            o = a[3:2];
            ofr = ar[3:2];
            if (fetch_word_rdy)
                o = fetch_word;
            i = a[11:4];
            ir = ar[11:4];
            t = a[31:12];
            if (rewrite)
                t = tag_rewrite;
            tr = ar[31:12];
            tag = t;
            tag_reg = tr;
            index = i;
            index_reg = ir;
            offset = o;
            offset_reg = ofr;
            byte = b;
            byte_reg = br;
        end

endmodule