hazard_ctrl.v

基于4个mips核的noc设计

module HAZARD_CTRL(Hazard, CtrlRegDst, CtrlRegValue, CtrlTarget, CtrlBranch, CtrlMemRead, CtrlMemtoReg, CtrlALUop, CtrlMemWrite, CtrlALUSrc, CtrlRegWrite, RegDst, RegValue, Target, Branch, MemRead, MemtoReg, ALUop, MemWrite, ALUSrc, RegWrite);
    input [0:0] Hazard;
    wire [0:0] Hazard;
    input [1:0] CtrlRegDst;
    wire [1:0] CtrlRegDst;
    input [0:0] CtrlRegValue;
    wire [0:0] CtrlRegValue;
    input [1:0] CtrlTarget;
    wire [1:0] CtrlTarget;
    input [1:0] CtrlBranch;
    wire [1:0] CtrlBranch;
    input [1:0] CtrlMemRead;
    wire [1:0] CtrlMemRead;
    input [1:0] CtrlMemtoReg;
    wire [1:0] CtrlMemtoReg;
    input [4:0] CtrlALUop;
    wire [4:0] CtrlALUop;
    input [1:0] CtrlMemWrite;
    wire [1:0] CtrlMemWrite;
    input [0:0] CtrlALUSrc;
    wire [0:0] CtrlALUSrc;
    input [0:0] CtrlRegWrite;
    wire [0:0] CtrlRegWrite;
    output [1:0] RegDst;
    reg [1:0] RegDst;
    output [0:0] RegValue;
    reg [0:0] RegValue;
    output [1:0] Target;
    reg [1:0] Target;
    output [1:0] Branch;
    reg [1:0] Branch;
    output [1:0] MemRead;
    reg [1:0] MemRead;
    output [1:0] MemtoReg;
    reg [1:0] MemtoReg;
    output [4:0] ALUop;
    reg [4:0] ALUop;
    output [1:0] MemWrite;
    reg [1:0] MemWrite;
    output [0:0] ALUSrc;
    reg [0:0] ALUSrc;
    output [0:0] RegWrite;
    reg [0:0] RegWrite;
    reg [0:0] hazard;
    reg [1:0] regdst;
    reg [0:0] regvalue;
    reg [1:0] target;
    reg [1:0] branch;
    reg [1:0] memread;
    reg [1:0] memtoreg;
    reg [4:0] aluop;
    reg [1:0] memwrite;
    reg [0:0] alusrc;
    reg [0:0] regwrite;
    
    always @(Hazard or CtrlRegDst or CtrlBranch or CtrlMemRead or CtrlMemtoReg or CtrlALUop or CtrlMemWrite or CtrlALUSrc or CtrlRegWrite or CtrlRegValue or CtrlTarget)
        begin : hazard_ctrl_thread
            hazard = Hazard;
            regdst = CtrlRegDst;
            regvalue = CtrlRegValue;
            target = CtrlTarget;
            branch = CtrlBranch;
            memread = CtrlMemRead;
            memtoreg = CtrlMemtoReg;
            aluop = CtrlALUop;
            memwrite = CtrlMemWrite;
            alusrc = CtrlALUSrc;
            regwrite = CtrlRegWrite;
            if (hazard == 1'b0)
            begin
                RegDst = regdst;
                RegValue = regvalue;
                Target = target;
                Branch = branch;
                MemRead = memread;
                MemtoReg = memtoreg;
                ALUop = aluop;
                MemWrite = memwrite;
                ALUSrc = alusrc;
                RegWrite = regwrite;
            end
            else
            begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                Branch = 2'b00;
                MemRead = 2'b00;
                MemtoReg = 2'b00;
                ALUop = 5'b00000;
                MemWrite = 2'b00;
                ALUSrc = 1'b0;
                RegWrite = 1'b0;
            end
        end

endmodule