bram16k_wrapper.v

基于4个mips核的noc设计

module BRAM16K_WRAPPER(addr, dout, din, w, r, clk, en, memwait, ADDR, DI00, DI01, DI02, DI03, DI04, DI05, DI06, DI07, EN, CLK, SSR, WE0, WE1, WE2, WE3, DO00, DO01, DO02, DO03, DO04, DO05, DO06, DO07);
    input [31:0] addr;
    wire [31:0] addr;
    output [31:0] dout;
    reg [31:0] dout;
    input [31:0] din;
    wire [31:0] din;
    input [1:0] w;
    wire [1:0] w;
    input [1:0] r;
    wire [1:0] r;
    input clk;
    wire clk;
    input [0:0] en;
    wire [0:0] en;
    output memwait;
    reg memwait;
    output [11:0] ADDR;
    reg [11:0] ADDR;
    output signed  [3:0] DI00;
    reg signed [3:0] DI00;
    output signed  [3:0] DI01;
    reg signed [3:0] DI01;
    output signed  [3:0] DI02;
    reg signed [3:0] DI02;
    output signed  [3:0] DI03;
    reg signed [3:0] DI03;
    output signed  [3:0] DI04;
    reg signed [3:0] DI04;
    output signed  [3:0] DI05;
    reg signed [3:0] DI05;
    output signed  [3:0] DI06;
    reg signed [3:0] DI06;
    output signed  [3:0] DI07;
    reg signed [3:0] DI07;
    output EN;
    reg EN;
    output CLK;
    reg CLK;
    output SSR;
    reg SSR;
    output WE0;
    reg WE0;
    output WE1;
    reg WE1;
    output WE2;
    reg WE2;
    output WE3;
    reg WE3;
    input signed  [3:0] DO00;
    wire signed [3:0] DO00;
    input signed  [3:0] DO01;
    wire signed [3:0] DO01;
    input signed  [3:0] DO02;
    wire signed [3:0] DO02;
    input signed  [3:0] DO03;
    wire signed [3:0] DO03;
    input signed  [3:0] DO04;
    wire signed [3:0] DO04;
    input signed  [3:0] DO05;
    wire signed [3:0] DO05;
    input signed  [3:0] DO06;
    wire signed [3:0] DO06;
    input signed  [3:0] DO07;
    wire signed [3:0] DO07;
    reg [1:0] ar;
    reg [1:0] r_reg;
    reg [1:0] w_reg;
    reg [1:0] byte_reg;
    reg [1:0] iw;
    reg [1:0] ir;
    reg [31:0] a;
    reg [11:0] a_13_2;
    reg [11:0] addr12;
    reg [31:0] dwr;
    reg [1:0] byteb;
    reg [1:0] byteno;
    reg [3:0] b0;
    reg [3:0] b1;
    reg byte_to_0;
    reg byte_to_1;
    reg byte_to_2;
    reg byte_to_3;
    reg [3:0] dwr0;
    reg [3:0] dwr1;
    reg [3:0] dwr2;
    reg [3:0] dwr3;
    reg [3:0] dwr4;
    reg [3:0] dwr5;
    reg [3:0] dwr6;
    reg [3:0] dwr7;
    reg signed [3:0] __tmp70;
    reg signed [3:0] __tmp71;
    reg signed [3:0] __tmp72;
    reg signed [3:0] __tmp73;
    reg signed [3:0] __tmp74;
    reg signed [3:0] __tmp75;
    reg signed [3:0] __tmp76;
    reg signed [3:0] __tmp77;
    reg e;
    reg [3:0] d0;
    reg [3:0] d1;
    reg [3:0] d2;
    reg [3:0] d3;
    reg [3:0] d4;
    reg [3:0] d5;
    reg [3:0] d6;
    reg [3:0] d7;
    reg [1:0] iw__1;
    reg [1:0] ir__2;
    reg byte_mode;
    reg [23:0] data24;
    reg [1:0] byteno__3;
    reg [7:0] msbyte;
    
    always @(posedge clk)
        begin : reg__20
            ar = addr[1:0];
            if (en[1'b0] != 0)
            begin
                r_reg <= r;
                w_reg <= w;
                byte_reg <= ar;
            end
        end

    
    always @(addr or din or w or r or en or clk)
        begin : in
            iw = w;
            ir = r;
            a = addr;
            a_13_2 = a[13:2];
            addr12 = a_13_2;
            ADDR = addr12;
            dwr = din;
            byteb = a[1:0];
            byteno = byteb;
            b0 = dwr[7:4];
            b1 = dwr[3:0];
            byte_to_0 = iw == 2'b10 && byteno == 2'b00;
            byte_to_1 = iw == 2'b10 && byteno == 2'b01;
            byte_to_2 = iw == 2'b10 && byteno == 2'b10;
            byte_to_3 = iw == 2'b10 && byteno == 2'b11;
            dwr0 = dwr[31:28];
            dwr1 = dwr[27:24];
            dwr2 = dwr[23:20];
            dwr3 = dwr[19:16];
            dwr4 = dwr[15:12];
            dwr5 = dwr[11:8];
            dwr6 = dwr[7:4];
            dwr7 = dwr[3:0];
            if (byte_to_0)
                __tmp70 = b0;
            else
                __tmp70 = dwr0;
            DI00 = __tmp70;
            if (byte_to_0)
                __tmp71 = b1;
            else
                __tmp71 = dwr1;
            DI01 = __tmp71;
            if (byte_to_1)
                __tmp72 = b0;
            else
                __tmp72 = dwr2;
            DI02 = __tmp72;
            if (byte_to_1)
                __tmp73 = b1;
            else
                __tmp73 = dwr3;
            DI03 = __tmp73;
            if (byte_to_2)
                __tmp74 = b0;
            else
                __tmp74 = dwr4;
            DI04 = __tmp74;
            if (byte_to_2)
                __tmp75 = b1;
            else
                __tmp75 = dwr5;
            DI05 = __tmp75;
            if (byte_to_3)
                __tmp76 = b0;
            else
                __tmp76 = dwr6;
            DI06 = __tmp76;
            if (byte_to_3)
                __tmp77 = b1;
            else
                __tmp77 = dwr7;
            DI07 = __tmp77;
            e = en[1'b0] != 0 && (ir != 2'b00 || iw != 2'b00);
            EN = e;
            WE0 = iw == 2'b01 || iw == 2'b10 && byte_to_0;
            WE1 = iw == 2'b01 || iw == 2'b10 && byte_to_1;
            WE2 = iw == 2'b01 || iw == 2'b10 && byte_to_2;
            WE3 = iw == 2'b01 || iw == 2'b10 && byte_to_3;
            SSR = 0;
            CLK = clk;
        end

    
    always @(DO00 or DO01 or DO02 or DO03 or DO04 or DO05 or DO06 or DO07 or w_reg or r_reg or byte_reg)
        begin : out
            d0 = DO00;
            d1 = DO01;
            d2 = DO02;
            d3 = DO03;
            d4 = DO04;
            d5 = DO05;
            d6 = DO06;
            d7 = DO07;
            iw__1 = w_reg;
            ir__2 = r_reg;
            byte_mode = iw__1 == 2'b10 || ir__2 == 2'b10;
            data24 = {d2, d3, d4, d5, d6, d7};
            if (byte_mode)
            begin
                byteno__3 = byte_reg;
                case (byteno__3) //synopsys parallel_case full_case
                0:                  msbyte = {d0, d1};
                1:                  msbyte = {d2, d3};
                2:                  msbyte = {d4, d5};
                3:                  msbyte = {d6, d7};
                endcase
            end
            else
                msbyte = {d0, d1};
            dout = {msbyte, data24};
            memwait = 0;
        end

endmodule