mem32k.v

基于4个mips核的noc设计

module MEM32K(addr, dout, din, ww, wb, r, clk, dbgDO, dbgADDR, dbgDI, dbgEN, dbgCLK, dbgWE, dbgRST);
    input [31:0] addr;
    wire [31:0] addr;
    output signed  [31:0] dout;
    input signed  [31:0] din;
    wire signed [31:0] din;
    input ww;
    wire ww;
    input wb;
    wire wb;
    input r;
    wire r;
    input clk;
    wire clk;
    output signed  [31:0] dbgDO;
    input [31:0] dbgADDR;
    wire [31:0] dbgADDR;
    input signed  [31:0] dbgDI;
    wire signed [31:0] dbgDI;
    input dbgEN;
    wire dbgEN;
    input dbgCLK;
    wire dbgCLK;
    input dbgWE;
    wire dbgWE;
    input dbgRST;
    wire dbgRST;
    wire [12:0] dADDR;
    wire signed [1:0] dDI00;
    wire signed [1:0] dDI01;
    wire signed [1:0] dDI02;
    wire signed [1:0] dDI03;
    wire signed [1:0] dDI04;
    wire signed [1:0] dDI05;
    wire signed [1:0] dDI06;
    wire signed [1:0] dDI07;
    wire signed [1:0] dDI08;
    wire signed [1:0] dDI09;
    wire signed [1:0] dDI10;
    wire signed [1:0] dDI11;
    wire signed [1:0] dDI12;
    wire signed [1:0] dDI13;
    wire signed [1:0] dDI14;
    wire signed [1:0] dDI15;
    wire dEN;
    wire dCLK;
    wire dSSR;
    wire dWE;
    wire signed [1:0] dDO00;
    wire signed [1:0] dDO01;
    wire signed [1:0] dDO02;
    wire signed [1:0] dDO03;
    wire signed [1:0] dDO04;
    wire signed [1:0] dDO05;
    wire signed [1:0] dDO06;
    wire signed [1:0] dDO07;
    wire signed [1:0] dDO08;
    wire signed [1:0] dDO09;
    wire signed [1:0] dDO10;
    wire signed [1:0] dDO11;
    wire signed [1:0] dDO12;
    wire signed [1:0] dDO13;
    wire signed [1:0] dDO14;
    wire signed [1:0] dDO15;
    wire [12:0] ADDR;
    wire signed [1:0] DI00;
    wire signed [1:0] DI01;
    wire signed [1:0] DI02;
    wire signed [1:0] DI03;
    wire signed [1:0] DI04;
    wire signed [1:0] DI05;
    wire signed [1:0] DI06;
    wire signed [1:0] DI07;
    wire signed [1:0] DI08;
    wire signed [1:0] DI09;
    wire signed [1:0] DI10;
    wire signed [1:0] DI11;
    wire signed [1:0] DI12;
    wire signed [1:0] DI13;
    wire signed [1:0] DI14;
    wire signed [1:0] DI15;
    wire EN;
    wire CLK;
    wire SSR;
    wire WE0;
    wire WE1;
    wire WE2;
    wire WE3;
    wire signed [1:0] DO00;
    wire signed [1:0] DO01;
    wire signed [1:0] DO02;
    wire signed [1:0] DO03;
    wire signed [1:0] DO04;
    wire signed [1:0] DO05;
    wire signed [1:0] DO06;
    wire signed [1:0] DO07;
    wire signed [1:0] DO08;
    wire signed [1:0] DO09;
    wire signed [1:0] DO10;
    wire signed [1:0] DO11;
    wire signed [1:0] DO12;
    wire signed [1:0] DO13;
    wire signed [1:0] DO14;
    wire signed [1:0] DO15;
    MEM32K_DBGWRAPPER dbgconv(.DO(dbgDO), .ADDR(dbgADDR), .DI(dbgDI), .EN(dbgEN), .CLK(dbgCLK), .WE(dbgWE), .RST(dbgRST), .dADDR(dADDR), .dDI00(dDI00), .dDI01(dDI01), .dDI02(dDI02), .dDI03(dDI03), .dDI04(dDI04), .dDI05(dDI05), .dDI06(dDI06), .dDI07(dDI07), .dDI08(dDI08), .dDI09(dDI09), .dDI10(dDI10), .dDI11(dDI11), .dDI12(dDI12), .dDI13(dDI13), .dDI14(dDI14), .dDI15(dDI15), .dEN(dEN), .dCLK(dCLK), .dSSR(dSSR), .dWE(dWE), .dDO00(dDO00), .dDO01(dDO01), .dDO02(dDO02), .dDO03(dDO03), .dDO04(dDO04), .dDO05(dDO05), .dDO06(dDO06), .dDO07(dDO07), .dDO08(dDO08), .dDO09(dDO09), .dDO10(dDO10), .dDO11(dDO11), .dDO12(dDO12), .dDO13(dDO13), .dDO14(dDO14), .dDO15(dDO15));
    MEM32K_WRAPPER conv(.addr(addr), .dout(dout), .din(din), .ww(ww), .wb(wb), .r(r), .clk(clk), .ADDR(ADDR), .DI00(DI00), .DI01(DI01), .DI02(DI02), .DI03(DI03), .DI04(DI04), .DI05(DI05), .DI06(DI06), .DI07(DI07), .DI08(DI08), .DI09(DI09), .DI10(DI10), .DI11(DI11), .DI12(DI12), .DI13(DI13), .DI14(DI14), .DI15(DI15), .EN(EN), .CLK(CLK), .SSR(SSR), .WE0(WE0), .WE1(WE1), .WE2(WE2), .WE3(WE3), .DO00(DO00), .DO01(DO01), .DO02(DO02), .DO03(DO03), .DO04(DO04), .DO05(DO05), .DO06(DO06), .DO07(DO07), .DO08(DO08), .DO09(DO09), .DO10(DO10), .DO11(DO11), .DO12(DO12), .DO13(DO13), .DO14(DO14), .DO15(DO15));
    RAMB16_S2_S2 bram15(.DOA(DO15), .ADDRA(ADDR), .DIA(DI15), .ENA(EN), .CLKA(CLK), .WEA(WE3), .SSRA(SSR), .DOB(dDO15), .ADDRB(dADDR), .DIB(dDI15), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram14(.DOA(DO14), .ADDRA(ADDR), .DIA(DI14), .ENA(EN), .CLKA(CLK), .WEA(WE3), .SSRA(SSR), .DOB(dDO14), .ADDRB(dADDR), .DIB(dDI14), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram13(.DOA(DO13), .ADDRA(ADDR), .DIA(DI13), .ENA(EN), .CLKA(CLK), .WEA(WE3), .SSRA(SSR), .DOB(dDO13), .ADDRB(dADDR), .DIB(dDI13), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram12(.DOA(DO12), .ADDRA(ADDR), .DIA(DI12), .ENA(EN), .CLKA(CLK), .WEA(WE3), .SSRA(SSR), .DOB(dDO12), .ADDRB(dADDR), .DIB(dDI12), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram11(.DOA(DO11), .ADDRA(ADDR), .DIA(DI11), .ENA(EN), .CLKA(CLK), .WEA(WE2), .SSRA(SSR), .DOB(dDO11), .ADDRB(dADDR), .DIB(dDI11), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram10(.DOA(DO10), .ADDRA(ADDR), .DIA(DI10), .ENA(EN), .CLKA(CLK), .WEA(WE2), .SSRA(SSR), .DOB(dDO10), .ADDRB(dADDR), .DIB(dDI10), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram09(.DOA(DO09), .ADDRA(ADDR), .DIA(DI09), .ENA(EN), .CLKA(CLK), .WEA(WE2), .SSRA(SSR), .DOB(dDO09), .ADDRB(dADDR), .DIB(dDI09), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram08(.DOA(DO08), .ADDRA(ADDR), .DIA(DI08), .ENA(EN), .CLKA(CLK), .WEA(WE2), .SSRA(SSR), .DOB(dDO08), .ADDRB(dADDR), .DIB(dDI08), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram07(.DOA(DO07), .ADDRA(ADDR), .DIA(DI07), .ENA(EN), .CLKA(CLK), .WEA(WE1), .SSRA(SSR), .DOB(dDO07), .ADDRB(dADDR), .DIB(dDI07), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram06(.DOA(DO06), .ADDRA(ADDR), .DIA(DI06), .ENA(EN), .CLKA(CLK), .WEA(WE1), .SSRA(SSR), .DOB(dDO06), .ADDRB(dADDR), .DIB(dDI06), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram05(.DOA(DO05), .ADDRA(ADDR), .DIA(DI05), .ENA(EN), .CLKA(CLK), .WEA(WE1), .SSRA(SSR), .DOB(dDO05), .ADDRB(dADDR), .DIB(dDI05), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram04(.DOA(DO04), .ADDRA(ADDR), .DIA(DI04), .ENA(EN), .CLKA(CLK), .WEA(WE1), .SSRA(SSR), .DOB(dDO04), .ADDRB(dADDR), .DIB(dDI04), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram03(.DOA(DO03), .ADDRA(ADDR), .DIA(DI03), .ENA(EN), .CLKA(CLK), .WEA(WE0), .SSRA(SSR), .DOB(dDO03), .ADDRB(dADDR), .DIB(dDI03), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram02(.DOA(DO02), .ADDRA(ADDR), .DIA(DI02), .ENA(EN), .CLKA(CLK), .WEA(WE0), .SSRA(SSR), .DOB(dDO02), .ADDRB(dADDR), .DIB(dDI02), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram01(.DOA(DO01), .ADDRA(ADDR), .DIA(DI01), .ENA(EN), .CLKA(CLK), .WEA(WE0), .SSRA(SSR), .DOB(dDO01), .ADDRB(dADDR), .DIB(dDI01), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
    RAMB16_S2_S2 bram00(.DOA(DO00), .ADDRA(ADDR), .DIA(DI00), .ENA(EN), .CLKA(CLK), .WEA(WE0), .SSRA(SSR), .DOB(dDO00), .ADDRB(dADDR), .DIB(dDI00), .ENB(dEN), .CLKB(dCLK), .WEB(dWE), .SSRB(dSSR));
endmodule