crossbar3x3.v

基于4个mips核的noc设计

module CROSSBAR3x3(clk, addr_0, addr_1, addr_2, conn_0, conn_1, conn_2, data_in_0, data_in_1, data_in_2, req_in_0, req_in_1, req_in_2, ack_in_0, ack_in_1, ack_in_2, data_out_0, data_out_1, data_out_2, req_out_0, req_out_1, req_out_2, ack_out_0, ack_out_1, ack_out_2);
    input clk;
    wire clk;
    input [1:0] addr_0;
    wire [1:0] addr_0;
    input [1:0] addr_1;
    wire [1:0] addr_1;
    input [1:0] addr_2;
    wire [1:0] addr_2;
    input conn_0;
    wire conn_0;
    input conn_1;
    wire conn_1;
    input conn_2;
    wire conn_2;
    input [17:0] data_in_0;
    wire [17:0] data_in_0;
    input [17:0] data_in_1;
    wire [17:0] data_in_1;
    input [17:0] data_in_2;
    wire [17:0] data_in_2;
    input req_in_0;
    wire req_in_0;
    input req_in_1;
    wire req_in_1;
    input req_in_2;
    wire req_in_2;
    input ack_in_0;
    wire ack_in_0;
    input ack_in_1;
    wire ack_in_1;
    input ack_in_2;
    wire ack_in_2;
    output [17:0] data_out_0;
    reg [17:0] data_out_0;
    output [17:0] data_out_1;
    reg [17:0] data_out_1;
    output [17:0] data_out_2;
    reg [17:0] data_out_2;
    output req_out_0;
    reg req_out_0;
    output req_out_1;
    reg req_out_1;
    output req_out_2;
    reg req_out_2;
    output ack_out_0;
    reg ack_out_0;
    output ack_out_1;
    reg ack_out_1;
    output ack_out_2;
    reg ack_out_2;
    reg [1:0] g0;
    reg [1:0] grant0;
    reg [1:0] g1;
    reg [1:0] grant1;
    reg [1:0] g2;
    reg [1:0] grant2;
    reg [17:0] zero;
    reg c00;
    reg c01;
    reg c02;
    reg c10;
    reg c11;
    reg c12;
    reg c20;
    reg c21;
    reg c22;
    reg [17:0] __tmp61;
    reg [17:0] __tmp62;
    reg [17:0] __tmp63;
    reg [17:0] __tmp64;
    reg [17:0] __tmp65;
    reg [17:0] __tmp66;
    reg [17:0] __tmp67;
    reg [17:0] __tmp68;
    reg [17:0] __tmp69;
    reg signed [31:0] __tmp70;
    reg signed [31:0] __tmp71;
    reg signed [31:0] __tmp72;
    reg signed [31:0] __tmp73;
    reg signed [31:0] __tmp74;
    reg signed [31:0] __tmp75;
    reg signed [31:0] __tmp76;
    reg signed [31:0] __tmp77;
    reg signed [31:0] __tmp78;
    reg signed [31:0] __tmp79;
    reg signed [31:0] __tmp80;
    reg signed [31:0] __tmp81;
    reg signed [31:0] __tmp82;
    reg signed [31:0] __tmp83;
    reg signed [31:0] __tmp84;
    reg signed [31:0] __tmp85;
    reg signed [31:0] __tmp86;
    reg signed [31:0] __tmp87;
    reg [1:0] a0;
    reg [1:0] a1;
    reg [1:0] a2;
    reg [1:0] g0__1;
    reg [1:0] g1__2;
    reg [1:0] g2__3;
    reg [1:0] rr;
    reg [1:0] round_robin;
    reg rrinc;
    reg c0;
    reg c1;
    reg c2;
    reg c00__4;
    reg c01__5;
    reg c02__6;
    reg c10__7;
    reg c11__8;
    reg c12__9;
    reg c20__10;
    reg c21__11;
    reg c22__12;
    reg [1:0] __tmp88;
    reg [1:0] __tmp89;
    reg [1:0] __tmp90;
    reg [1:0] __tmp91;
    reg [1:0] __tmp92;
    reg [1:0] __tmp93;
    reg [1:0] __tmp94;
    reg [1:0] __tmp95;
    reg [1:0] __tmp96;
    reg rr_inc;
    
    always @(data_in_0 or data_in_1 or data_in_2 or req_in_0 or req_in_1 or req_in_2 or ack_in_0 or ack_in_1 or ack_in_2 or grant0 or grant1 or grant2)
        begin : crossbar_process
            g0 = grant0;
            g1 = grant1;
            g2 = grant2;
            zero = 18'b000000000000000000;
            c00 = g0 == 2'b01;
            c01 = g1 == 2'b01;
            c02 = g2 == 2'b01;
            c10 = g0 == 2'b10;
            c11 = g1 == 2'b10;
            c12 = g2 == 2'b10;
            c20 = g0 == 2'b11;
            c21 = g1 == 2'b11;
            c22 = g2 == 2'b11;
            if (c00)
                __tmp61 = data_in_0;
            else
            begin
                if (c10)
                    __tmp62 = data_in_1;
                else
                begin
                    if (c20)
                        __tmp63 = data_in_2;
                    else
                        __tmp63 = zero;
                    __tmp62 = __tmp63;
                end
                __tmp61 = __tmp62;
            end
            data_out_0 = __tmp61;
            if (c01)
                __tmp64 = data_in_0;
            else
            begin
                if (c11)
                    __tmp65 = data_in_1;
                else
                begin
                    if (c21)
                        __tmp66 = data_in_2;
                    else
                        __tmp66 = zero;
                    __tmp65 = __tmp66;
                end
                __tmp64 = __tmp65;
            end
            data_out_1 = __tmp64;
            if (c02)
                __tmp67 = data_in_0;
            else
            begin
                if (c12)
                    __tmp68 = data_in_1;
                else
                begin
                    if (c22)
                        __tmp69 = data_in_2;
                    else
                        __tmp69 = zero;
                    __tmp68 = __tmp69;
                end
                __tmp67 = __tmp68;
            end
            data_out_2 = __tmp67;
            if (c00)
                __tmp70 = req_in_0;
            else
            begin
                if (c10)
                    __tmp71 = req_in_1;
                else
                begin
                    if (c20)
                        __tmp72 = req_in_2;
                    else
                        __tmp72 = 0;
                    __tmp71 = __tmp72;
                end
                __tmp70 = __tmp71;
            end
            req_out_0 = __tmp70;
            if (c01)
                __tmp73 = req_in_0;
            else
            begin
                if (c11)
                    __tmp74 = req_in_1;
                else
                begin
                    if (c21)
                        __tmp75 = req_in_2;
                    else
                        __tmp75 = 0;
                    __tmp74 = __tmp75;
                end
                __tmp73 = __tmp74;
            end
            req_out_1 = __tmp73;
            if (c02)
                __tmp76 = req_in_0;
            else
            begin
                if (c12)
                    __tmp77 = req_in_1;
                else
                begin
                    if (c22)
                        __tmp78 = req_in_2;
                    else
                        __tmp78 = 0;
                    __tmp77 = __tmp78;
                end
                __tmp76 = __tmp77;
            end
            req_out_2 = __tmp76;
            if (c00)
                __tmp79 = ack_in_0;
            else
            begin
                if (c01)
                    __tmp80 = ack_in_1;
                else
                begin
                    if (c02)
                        __tmp81 = ack_in_2;
                    else
                        __tmp81 = 0;
                    __tmp80 = __tmp81;
                end
                __tmp79 = __tmp80;
            end
            ack_out_0 = __tmp79;
            if (c10)
                __tmp82 = ack_in_0;
            else
            begin
                if (c11)
                    __tmp83 = ack_in_1;
                else
                begin
                    if (c12)
                        __tmp84 = ack_in_2;
                    else
                        __tmp84 = 0;
                    __tmp83 = __tmp84;
                end
                __tmp82 = __tmp83;
            end
            ack_out_1 = __tmp82;
            if (c20)
                __tmp85 = ack_in_0;
            else
            begin
                if (c21)
                    __tmp86 = ack_in_1;
                else
                begin
                    if (c22)
                        __tmp87 = ack_in_2;
                    else
                        __tmp87 = 0;
                    __tmp86 = __tmp87;
                end
                __tmp85 = __tmp86;
            end
            ack_out_2 = __tmp85;
        end

    
    always @(posedge clk)
        begin : arbiter_process
            a0 = addr_0;
            a1 = addr_1;
            a2 = addr_2;
            g0__1 = grant0;
            g1__2 = grant1;
            g2__3 = grant2;
            rr = round_robin;
            rrinc = 0;
            c0 = conn_0 == 1;
            c1 = conn_1 == 1;
            c2 = conn_2 == 1;
            c00__4 = c0 && a0 == 2'b01;
            c01__5 = c0 && a0 == 2'b10;
            c02__6 = c0 && a0 == 2'b11;
            c10__7 = c1 && a1 == 2'b01;
            c11__8 = c1 && a1 == 2'b10;
            c12__9 = c1 && a1 == 2'b11;
            c20__10 = c2 && a2 == 2'b01;
            c21__11 = c2 && a2 == 2'b10;
            c22__12 = c2 && a2 == 2'b11;
            if (g0__1 != 2'b00)
            begin
                if (g0__1 == 2'b01 && !c0 || g0__1 == 2'b10 && !c1 || g0__1 == 2'b11 && !c2)
                    g0__1 = 2'b00;
            end
            else
            begin
                if (c00__4 && rr == 2'b00)
                begin
                    rrinc = 1;
                    g0__1 = 2'b01;
                end
                else
                begin
                    if (c10__7 && rr == 2'b01)
                    begin
                        rrinc = 1;
                        g0__1 = 2'b10;
                    end
                    else
                    begin
                        if (c20__10 && rr == 2'b10)
                        begin
                            rrinc = 1;
                            g0__1 = 2'b11;
                        end
                        else
                        begin
                            if (c00__4)
                                __tmp88 = 2'b01;
                            else
                            begin
                                if (c10__7)
                                    __tmp89 = 2'b10;
                                else
                                begin
                                    if (c20__10)
                                        __tmp90 = 2'b11;
                                    else
                                        __tmp90 = 2'b00;
                                    __tmp89 = __tmp90;
                                end
                                __tmp88 = __tmp89;
                            end
                            g0__1 = __tmp88;
                        end
                    end
                end
            end
            if (g1__2 != 2'b00)
            begin
                if (g1__2 == 2'b01 && !c0 || g1__2 == 2'b10 && !c1 || g1__2 == 2'b11 && !c2)
                    g1__2 = 2'b00;
            end
            else
            begin
                if (c01__5 && rr == 2'b00)
                begin
                    rrinc = 1;
                    g1__2 = 2'b01;
                end
                else
                begin
                    if (c11__8 && rr == 2'b01)
                    begin
                        rrinc = 1;
                        g1__2 = 2'b10;
                    end
                    else
                    begin
                        if (c21__11 && rr == 2'b10)
                        begin
                            rrinc = 1;
                            g1__2 = 2'b11;
                        end
                        else
                        begin
                            if (c01__5)
                                __tmp91 = 2'b01;
                            else
                            begin
                                if (c11__8)
                                    __tmp92 = 2'b10;
                                else
                                begin
                                    if (c21__11)
                                        __tmp93 = 2'b11;
                                    else
                                        __tmp93 = 2'b00;
                                    __tmp92 = __tmp93;
                                end
                                __tmp91 = __tmp92;
                            end
                            g1__2 = __tmp91;
                        end
                    end
                end
            end
            if (g2__3 != 2'b00)
            begin
                if (g2__3 == 2'b01 && !c0 || g2__3 == 2'b10 && !c1 || g2__3 == 2'b11 && !c2)
                    g2__3 = 2'b00;
            end
            else
            begin
                if (c02__6 && rr == 2'b00)
                begin
                    rrinc = 1;
                    g2__3 = 2'b01;
                end
                else
                begin
                    if (c12__9 && rr == 2'b01)
                    begin
                        rrinc = 1;
                        g2__3 = 2'b10;
                    end
                    else
                    begin
                        if (c22__12 && rr == 2'b10)
                        begin
                            rrinc = 1;
                            g2__3 = 2'b11;
                        end
                        else
                        begin
                            if (c02__6)
                                __tmp94 = 2'b01;
                            else
                            begin
                                if (c12__9)
                                    __tmp95 = 2'b10;
                                else
                                begin
                                    if (c22__12)
                                        __tmp96 = 2'b11;
                                    else
                                        __tmp96 = 2'b00;
                                    __tmp95 = __tmp96;
                                end
                                __tmp94 = __tmp95;
                            end
                            g2__3 = __tmp94;
                        end
                    end
                end
            end
            grant0 <= g0__1;
            grant1 <= g1__2;
            grant2 <= g2__3;
            rr_inc <= rrinc;
        end

    
    always @(posedge clk)
        begin : round_robin_process
            if (rr_inc)
                round_robin <= 2'b01 + round_robin;
        end

endmodule