network2x2.v

基于4个mips核的noc设计

module NETWORK2x2(clk, rst, x0y0din, x0y0dout, x0y0req_net, x0y0ack_net, x0y0ack_dp, x0y0req_dp, x0y1din, x0y1dout, x0y1req_net, x0y1ack_net, x0y1ack_dp, x0y1req_dp, x1y0din, x1y0dout, x1y0req_net, x1y0ack_net, x1y0ack_dp, x1y0req_dp, x1y1din, x1y1dout, x1y1req_net, x1y1ack_net, x1y1ack_dp, x1y1req_dp);
    input clk;
    wire clk;
    input rst;
    wire rst;
    input [17:0] x0y0din;
    wire [17:0] x0y0din;
    output [17:0] x0y0dout;
    input x0y0req_net;
    wire x0y0req_net;
    output x0y0ack_net;
    input x0y0ack_dp;
    wire x0y0ack_dp;
    output x0y0req_dp;
    input [17:0] x0y1din;
    wire [17:0] x0y1din;
    output [17:0] x0y1dout;
    input x0y1req_net;
    wire x0y1req_net;
    output x0y1ack_net;
    input x0y1ack_dp;
    wire x0y1ack_dp;
    output x0y1req_dp;
    input [17:0] x1y0din;
    wire [17:0] x1y0din;
    output [17:0] x1y0dout;
    input x1y0req_net;
    wire x1y0req_net;
    output x1y0ack_net;
    input x1y0ack_dp;
    wire x1y0ack_dp;
    output x1y0req_dp;
    input [17:0] x1y1din;
    wire [17:0] x1y1din;
    output [17:0] x1y1dout;
    input x1y1req_net;
    wire x1y1req_net;
    output x1y1ack_net;
    input x1y1ack_dp;
    wire x1y1ack_dp;
    output x1y1req_dp;
    wire [7:0] addr1;
    wire [17:0] x0y1_x1y1_data;
    wire [17:0] x1y0_x1y1_data;
    wire [17:0] x1y1_x0y1_data;
    wire [17:0] x1y1_x1y0_data;
    wire x0y1_x1y1_ch0req;
    wire x0y1_x1y1_ch1req;
    wire x1y1_x0y1_ch0ack;
    wire x1y1_x0y1_ch1ack;
    wire x1y1_x0y1_ch0req;
    wire x1y1_x0y1_ch1req;
    wire x0y1_x1y1_ch0ack;
    wire x0y1_x1y1_ch1ack;
    wire x1y0_x1y1_ch0req;
    wire x1y0_x1y1_ch1req;
    wire x1y1_x1y0_ch0ack;
    wire x1y1_x1y0_ch1ack;
    wire x1y1_x1y0_ch0req;
    wire x1y1_x1y0_ch1req;
    wire x1y0_x1y1_ch0ack;
    wire x1y0_x1y1_ch1ack;
    wire [7:0] addr0;
    wire [17:0] x0y0_x1y0_data;
    wire [17:0] x1y0_x0y0_data;
    wire x0y0_x1y0_ch0req;
    wire x0y0_x1y0_ch1req;
    wire x1y0_x0y0_ch0ack;
    wire x1y0_x0y0_ch1ack;
    wire x1y0_x0y0_ch0req;
    wire x1y0_x0y0_ch1req;
    wire x0y0_x1y0_ch0ack;
    wire x0y0_x1y0_ch1ack;
    wire [17:0] x0y0_x0y1_data;
    wire [17:0] x0y1_x0y0_data;
    wire x0y0_x0y1_ch0req;
    wire x0y0_x0y1_ch1req;
    wire x0y1_x0y0_ch0ack;
    wire x0y1_x0y0_ch1ack;
    wire x0y1_x0y0_ch0req;
    wire x0y1_x0y0_ch1req;
    wire x0y0_x0y1_ch0ack;
    wire x0y0_x0y1_ch1ack;
    ECUBE_ROUTER x1y1(.clk(clk), .rst(rst), .xaddr(addr1), .yaddr(addr1), .xin(x0y1_x1y1_data), .yin(x1y0_x1y1_data), .din(x1y1din), .xout(x1y1_x0y1_data), .yout(x1y1_x1y0_data), .dout(x1y1dout), .dreq_in(x1y1req_net), .dack_in(x1y1ack_dp), .dreq_out(x1y1req_dp), .dack_out(x1y1ack_net), .x0req_in(x0y1_x1y1_ch0req), .x1req_in(x0y1_x1y1_ch1req), .x0ack_in(x1y1_x0y1_ch0ack), .x1ack_in(x1y1_x0y1_ch1ack), .x0req_out(x1y1_x0y1_ch0req), .x1req_out(x1y1_x0y1_ch1req), .x0ack_out(x0y1_x1y1_ch0ack), .x1ack_out(x0y1_x1y1_ch1ack), .y0req_in(x1y0_x1y1_ch0req), .y1req_in(x1y0_x1y1_ch1req), .y0ack_in(x1y1_x1y0_ch0ack), .y1ack_in(x1y1_x1y0_ch1ack), .y0req_out(x1y1_x1y0_ch0req), .y1req_out(x1y1_x1y0_ch1req), .y0ack_out(x1y0_x1y1_ch0ack), .y1ack_out(x1y0_x1y1_ch1ack));
    ECUBE_ROUTER x1y0(.clk(clk), .rst(rst), .xaddr(addr1), .yaddr(addr0), .xin(x0y0_x1y0_data), .yin(x1y1_x1y0_data), .din(x1y0din), .xout(x1y0_x0y0_data), .yout(x1y0_x1y1_data), .dout(x1y0dout), .dreq_in(x1y0req_net), .dack_in(x1y0ack_dp), .dreq_out(x1y0req_dp), .dack_out(x1y0ack_net), .x0req_in(x0y0_x1y0_ch0req), .x1req_in(x0y0_x1y0_ch1req), .x0ack_in(x1y0_x0y0_ch0ack), .x1ack_in(x1y0_x0y0_ch1ack), .x0req_out(x1y0_x0y0_ch0req), .x1req_out(x1y0_x0y0_ch1req), .x0ack_out(x0y0_x1y0_ch0ack), .x1ack_out(x0y0_x1y0_ch1ack), .y0req_in(x1y1_x1y0_ch0req), .y1req_in(x1y1_x1y0_ch1req), .y0ack_in(x1y0_x1y1_ch0ack), .y1ack_in(x1y0_x1y1_ch1ack), .y0req_out(x1y0_x1y1_ch0req), .y1req_out(x1y0_x1y1_ch1req), .y0ack_out(x1y1_x1y0_ch0ack), .y1ack_out(x1y1_x1y0_ch1ack));
    ECUBE_ROUTER x0y1(.clk(clk), .rst(rst), .xaddr(addr0), .yaddr(addr1), .xin(x1y1_x0y1_data), .yin(x0y0_x0y1_data), .din(x0y1din), .xout(x0y1_x1y1_data), .yout(x0y1_x0y0_data), .dout(x0y1dout), .dreq_in(x0y1req_net), .dack_in(x0y1ack_dp), .dreq_out(x0y1req_dp), .dack_out(x0y1ack_net), .x0req_in(x1y1_x0y1_ch0req), .x1req_in(x1y1_x0y1_ch1req), .x0ack_in(x0y1_x1y1_ch0ack), .x1ack_in(x0y1_x1y1_ch1ack), .x0req_out(x0y1_x1y1_ch0req), .x1req_out(x0y1_x1y1_ch1req), .x0ack_out(x1y1_x0y1_ch0ack), .x1ack_out(x1y1_x0y1_ch1ack), .y0req_in(x0y0_x0y1_ch0req), .y1req_in(x0y0_x0y1_ch1req), .y0ack_in(x0y1_x0y0_ch0ack), .y1ack_in(x0y1_x0y0_ch1ack), .y0req_out(x0y1_x0y0_ch0req), .y1req_out(x0y1_x0y0_ch1req), .y0ack_out(x0y0_x0y1_ch0ack), .y1ack_out(x0y0_x0y1_ch1ack));
    ECUBE_ROUTER x0y0(.clk(clk), .rst(rst), .xaddr(addr0), .yaddr(addr0), .xin(x1y0_x0y0_data), .yin(x0y1_x0y0_data), .din(x0y0din), .xout(x0y0_x1y0_data), .yout(x0y0_x0y1_data), .dout(x0y0dout), .dreq_in(x0y0req_net), .dack_in(x0y0ack_dp), .dreq_out(x0y0req_dp), .dack_out(x0y0ack_net), .x0req_in(x1y0_x0y0_ch0req), .x1req_in(x1y0_x0y0_ch1req), .x0ack_in(x0y0_x1y0_ch0ack), .x1ack_in(x0y0_x1y0_ch1ack), .x0req_out(x0y0_x1y0_ch0req), .x1req_out(x0y0_x1y0_ch1req), .x0ack_out(x1y0_x0y0_ch0ack), .x1ack_out(x1y0_x0y0_ch1ack), .y0req_in(x0y1_x0y0_ch0req), .y1req_in(x0y1_x0y0_ch1req), .y0ack_in(x0y0_x0y1_ch0ack), .y1ack_in(x0y0_x0y1_ch1ack), .y0req_out(x0y0_x0y1_ch0req), .y1req_out(x0y0_x0y1_ch1req), .y0ack_out(x0y1_x0y0_ch0ack), .y1ack_out(x0y1_x0y0_ch1ack));
    assign addr1 = 8'b00000001;
    assign addr0 = 8'b00000000;
endmodule