reg_disable.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 15 行

module REG_DISABLE(memwait, en, disable__22);
    input memwait;
    wire memwait;
    input [0:0] en;
    wire [0:0] en;
    output disable__22;
    reg disable__22;
    
    always @(memwait or en)
        begin : out
            disable__22 = memwait || en[1'b0] == 0;
        end

endmodule