shiftleft.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 17 行

module SHIFTLEFT(in, out);
    input [31:0] in;
    wire [31:0] in;
    output [31:0] out;
    reg [31:0] out;
    reg [31:0] a;
    reg [31:0] b;
    
    always @(in)
        begin : shiftleft_thread
            a = in;
            b = (a << 2);
            out = b;
        end

endmodule