decoder.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 52 行

module DECODER(instr, instr_31_26, instr_25_0, instr_25_21, instr_20_16, instr_15_11, instr_15_0, instr_10_6, instr_5_0);
    input [31:0] instr;
    wire [31:0] instr;
    output [5:0] instr_31_26;
    reg [5:0] instr_31_26;
    output [31:0] instr_25_0;
    reg [31:0] instr_25_0;
    output [4:0] instr_25_21;
    reg [4:0] instr_25_21;
    output [4:0] instr_20_16;
    reg [4:0] instr_20_16;
    output [4:0] instr_15_11;
    reg [4:0] instr_15_11;
    output [15:0] instr_15_0;
    reg [15:0] instr_15_0;
    output [4:0] instr_10_6;
    reg [4:0] instr_10_6;
    output [5:0] instr_5_0;
    reg [5:0] instr_5_0;
    reg [31:0] t_instr;
    reg [5:0] t_instr_31_26;
    reg [31:0] t_instr_25_0;
    reg [4:0] t_instr_25_21;
    reg [4:0] t_instr_20_16;
    reg [4:0] t_instr_15_11;
    reg [15:0] t_instr_15_0;
    reg [4:0] t_instr_10_6;
    reg [5:0] t_instr_5_0;
    
    always @(instr)
        begin : decoder_thread
            t_instr = instr;
            t_instr_31_26 = t_instr[31:26];
            t_instr_25_0 = t_instr[25:0];
            t_instr_25_21 = t_instr[25:21];
            t_instr_20_16 = t_instr[20:16];
            t_instr_15_11 = t_instr[15:11];
            t_instr_15_0 = t_instr[15:0];
            t_instr_10_6 = t_instr[10:6];
            t_instr_5_0 = t_instr[5:0];
            instr_31_26 = t_instr_31_26;
            instr_25_0 = t_instr_25_0;
            instr_25_21 = t_instr_25_21;
            instr_20_16 = t_instr_20_16;
            instr_15_11 = t_instr_15_11;
            instr_15_0 = t_instr_15_0;
            instr_10_6 = t_instr_10_6;
            instr_5_0 = t_instr_5_0;
        end

endmodule