arbiter_channel_ctrl.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 77 行

module ARBITER_CHANNEL_CTRL(clk, rst, reqin, ackin, reqout, ackout, arb_req, arb_grant);
    input clk;
    wire clk;
    input rst;
    wire rst;
    input reqin;
    wire reqin;
    input ackin;
    wire ackin;
    output reqout;
    reg reqout;
    output ackout;
    reg ackout;
    output arb_req;
    reg arb_req;
    input arb_grant;
    wire arb_grant;
    reg reqout_v;
    reg arb_req_v;
    reg [1:0] next_state;
    reg [1:0] current_state;
    
    always @(current_state or reqin or arb_grant)
        begin : logic
            reqout_v = 0;
            arb_req_v = 0;
            next_state = 2'b00;
            case (current_state) //synopsys parallel_case full_case
            0:              if (reqin)
            begin
                next_state = 2'b01;
                arb_req_v = 1;
            end
            else
                next_state = 2'b00;
            1:  begin
                arb_req_v = 1;
                if (arb_grant)
                begin
                    reqout_v = 1;
                    next_state = 2'b10;
                end
                else
                begin
                    arb_req_v = 1;
                    next_state = 2'b01;
                end
            end
            2:              if (reqin)
            begin
                reqout_v = 1;
                next_state = 2'b10;
            end
            else
                next_state = 2'b00;
            endcase
            reqout = reqout_v;
            arb_req = arb_req_v;
        end

    
    always @(posedge clk or posedge rst)
        begin : change_state
            if (rst)
                current_state <= 2'b00;
            else
                current_state <= next_state;
        end

    
    always @(ackin)
        begin : forward_ack
            ackout = ackin;
        end

endmodule