bram512x32.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 34 行

module BRAM512x32(r_addr, r_data, w_addr, w_data, w, clk);
    input [4:0] r_addr;
    wire [4:0] r_addr;
    output [31:0] r_data;
    input [4:0] w_addr;
    wire [4:0] w_addr;
    input [31:0] w_data;
    wire [31:0] w_data;
    input [0:0] w;
    wire [0:0] w;
    input clk;
    wire clk;
    wire signed [31:0] DOA;
    wire signed [3:0] DOPA;
    wire [8:0] ADDRA;
    wire signed [31:0] DIA;
    wire signed [3:0] DIPA;
    wire ENA;
    wire CLKA;
    wire WEA;
    wire SSRA;
    wire signed [31:0] DOB;
    wire signed [3:0] DOPB;
    wire [8:0] ADDRB;
    wire signed [31:0] DIB;
    wire signed [3:0] DIPB;
    wire ENB;
    wire CLKB;
    wire WEB;
    wire SSRB;
    BRAM512x32_CONV conv(.r_addr(r_addr), .r_data(r_data), .w_addr(w_addr), .w_data(w_data), .w(w), .clk(clk), .DOA(DOA), .DOPA(DOPA), .ADDRA(ADDRA), .DIA(DIA), .DIPA(DIPA), .ENA(ENA), .CLKA(CLKA), .WEA(WEA), .SSRA(SSRA), .DOB(DOB), .DOPB(DOPB), .ADDRB(ADDRB), .DIB(DIB), .DIPB(DIPB), .ENB(ENB), .CLKB(CLKB), .WEB(WEB), .SSRB(SSRB));
    RAMB16_S36_S36 bram(.DOA(DOA), .DOPA(DOPA), .ADDRA(ADDRA), .DIA(DIA), .DIPA(DIPA), .ENA(ENA), .CLKA(CLKA), .WEA(WEA), .SSRA(SSRA), .DOB(DOB), .DOPB(DOPB), .ADDRB(ADDRB), .DIB(DIB), .DIPB(DIPB), .ENB(ENB), .CLKB(CLKB), .WEB(WEB), .SSRB(SSRB));
endmodule