ecube_router.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 55 行

module ECUBE_ROUTER(clk, rst, xaddr, yaddr, xin, yin, din, xout, yout, dout, dreq_in, dack_in, dreq_out, dack_out, x0req_in, x1req_in, x0ack_in, x1ack_in, x0req_out, x1req_out, x0ack_out, x1ack_out, y0req_in, y1req_in, y0ack_in, y1ack_in, y0req_out, y1req_out, y0ack_out, y1ack_out);
    input clk;
    wire clk;
    input rst;
    wire rst;
    input [7:0] xaddr;
    wire [7:0] xaddr;
    input [7:0] yaddr;
    wire [7:0] yaddr;
    input [17:0] xin;
    wire [17:0] xin;
    input [17:0] yin;
    wire [17:0] yin;
    input [17:0] din;
    wire [17:0] din;
    output [17:0] xout;
    output [17:0] yout;
    output [17:0] dout;
    input dreq_in;
    wire dreq_in;
    input dack_in;
    wire dack_in;
    output dreq_out;
    output dack_out;
    input x0req_in;
    wire x0req_in;
    input x1req_in;
    wire x1req_in;
    input x0ack_in;
    wire x0ack_in;
    input x1ack_in;
    wire x1ack_in;
    output x0req_out;
    output x1req_out;
    output x0ack_out;
    output x1ack_out;
    input y0req_in;
    wire y0req_in;
    input y1req_in;
    wire y1req_in;
    input y0ack_in;
    wire y0ack_in;
    input y1ack_in;
    wire y1ack_in;
    output y0req_out;
    output y1req_out;
    output y0ack_out;
    output y1ack_out;
    wire [17:0] xydata;
    wire xyreq;
    wire xyack;
    ECUBE_ROUTER_1DIM yrouter(.clk(clk), .rst(rst), .addr(yaddr), .xin(yin), .din(xydata), .xout(yout), .dout(dout), .dreq_in(xyreq), .dack_in(dack_in), .dreq_out(dreq_out), .dack_out(xyack), .x0req_in(y0req_in), .x1req_in(y1req_in), .x0ack_in(y0ack_in), .x1ack_in(y1ack_in), .x0req_out(y0req_out), .x1req_out(y1req_out), .x0ack_out(y0ack_out), .x1ack_out(y1ack_out));
    ECUBE_ROUTER_1DIM xrouter(.clk(clk), .rst(rst), .addr(xaddr), .xin(xin), .din(din), .xout(xout), .dout(xydata), .dreq_in(dreq_in), .dack_in(xyack), .dreq_out(xyreq), .dack_out(dack_out), .x0req_in(x0req_in), .x1req_in(x1req_in), .x0ack_in(x0ack_in), .x1ack_in(x1ack_in), .x0req_out(x0req_out), .x1req_out(x1req_out), .x0ack_out(x0ack_out), .x1ack_out(x1ack_out));
endmodule