cache_mainmem.v

基于4个mips核的noc设计

module CACHE_MAINMEM(clk, addr0, addr1, din0, din1, dout, ww0, ww1, wb0, wb1, r0, r1, rdy0, rdy1, ramDO, ramADDR, ramDI, ramEN, ramCLK, ramWE, ramRST);
    input clk;
    wire clk;
    input [31:0] addr0;
    wire [31:0] addr0;
    input [31:0] addr1;
    wire [31:0] addr1;
    input [31:0] din0;
    wire [31:0] din0;
    input [31:0] din1;
    wire [31:0] din1;
    output [31:0] dout;
    input ww0;
    wire ww0;
    input ww1;
    wire ww1;
    input wb0;
    wire wb0;
    input wb1;
    wire wb1;
    input r0;
    wire r0;
    input r1;
    wire r1;
    output rdy0;
    output rdy1;
    output signed  [31:0] ramDO;
    input [31:0] ramADDR;
    wire [31:0] ramADDR;
    input signed  [31:0] ramDI;
    wire signed [31:0] ramDI;
    input ramEN;
    wire ramEN;
    input ramCLK;
    wire ramCLK;
    input ramWE;
    wire ramWE;
    input ramRST;
    wire ramRST;
    wire [31:0] mem_addr;
    wire signed [31:0] mem_dout;
    wire signed [31:0] mem_din;
    wire mem_ww;
    wire mem_wb;
    wire mem_r;
    wire mem_clk;
    MEM32K memory(.addr(mem_addr), .dout(mem_dout), .din(mem_din), .ww(mem_ww), .wb(mem_wb), .r(mem_r), .clk(mem_clk), .dbgDO(ramDO), .dbgADDR(ramADDR), .dbgDI(ramDI), .dbgEN(ramEN), .dbgCLK(ramCLK), .dbgWE(ramWE), .dbgRST(ramRST));
    CACHE_MAINMEM_ARBITER arbiter(.clk(clk), .addr0(addr0), .addr1(addr1), .din0(din0), .din1(din1), .dout(dout), .ww0(ww0), .ww1(ww1), .wb0(wb0), .wb1(wb1), .r0(r0), .r1(r1), .rdy0(rdy0), .rdy1(rdy1), .mem_addr(mem_addr), .mem_dout(mem_dout), .mem_din(mem_din), .mem_wb(mem_wb), .mem_ww(mem_ww), .mem_r(mem_r), .mem_clk(mem_clk));
endmodule