bram512x32_conv.v

基于4个mips核的noc设计

module BRAM512x32_CONV(r_addr, r_data, w_addr, w_data, w, clk, DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
    input [4:0] r_addr;
    wire [4:0] r_addr;
    output [31:0] r_data;
    reg [31:0] r_data;
    input [4:0] w_addr;
    wire [4:0] w_addr;
    input [31:0] w_data;
    wire [31:0] w_data;
    input [0:0] w;
    wire [0:0] w;
    input clk;
    wire clk;
    input signed  [31:0] DOA;
    wire signed [31:0] DOA;
    input signed  [3:0] DOPA;
    wire signed [3:0] DOPA;
    output [8:0] ADDRA;
    reg [8:0] ADDRA;
    output signed  [31:0] DIA;
    reg signed [31:0] DIA;
    output signed  [3:0] DIPA;
    reg signed [3:0] DIPA;
    output ENA;
    reg ENA;
    output CLKA;
    reg CLKA;
    output WEA;
    reg WEA;
    output SSRA;
    reg SSRA;
    input signed  [31:0] DOB;
    wire signed [31:0] DOB;
    input signed  [3:0] DOPB;
    wire signed [3:0] DOPB;
    output [8:0] ADDRB;
    reg [8:0] ADDRB;
    output signed  [31:0] DIB;
    reg signed [31:0] DIB;
    output signed  [3:0] DIPB;
    reg signed [3:0] DIPB;
    output ENB;
    reg ENB;
    output CLKB;
    reg CLKB;
    output WEB;
    reg WEB;
    output SSRB;
    reg SSRB;
    reg c;
    reg [3:0] zero4;
    reg [8:0] w_addr9;
    reg [8:0] r_addr9;
    reg [31:0] dwr;
    reg [31:0] data;
    
    always @(clk)
        begin : clock
            c = clk;
            CLKA = c;
            CLKB = !c;
        end

    
    always @(r_addr or w_addr or w_data or w)
        begin : in
            zero4 = 4'b0000;
            w_addr9 = {zero4, w_addr};
            r_addr9 = {zero4, r_addr};
            ADDRA = r_addr9;
            ADDRB = w_addr9;
            dwr = w_data;
            DIB = dwr;
            DIPB = 4'sb0000;
            WEB = w[1'b0] != 0;
            DIA = 0;
            DIPA = 4'sb0000;
            WEA = 0;
            ENA = 1;
            ENB = 1;
            SSRA = 0;
            SSRB = 0;
        end

    
    always @(DOA or DOB or DOPA or DOPB)
        begin : out
            data = DOA;
            r_data = data;
        end

endmodule