cache_memory.v

基于4个mips核的noc设计

module CACHE_MEMORY(clk, din, valid_in, tagi, index, offset, we, en, dout, tago, valid);
    input clk;
    wire clk;
    input [31:0] din;
    wire [31:0] din;
    input valid_in;
    wire valid_in;
    input [19:0] tagi;
    wire [19:0] tagi;
    input [7:0] index;
    wire [7:0] index;
    input [1:0] offset;
    wire [1:0] offset;
    input we;
    wire we;
    input en;
    wire en;
    output [31:0] dout;
    output [19:0] tago;
    output valid;
    wire signed [31:0] DOA1;
    wire signed [3:0] DOPA1;
    wire [8:0] ADDRA1;
    wire signed [31:0] DIA1;
    wire signed [3:0] DIPA1;
    wire ENA1;
    wire CLKA1;
    wire WEA1;
    wire SSRA1;
    wire signed [31:0] DOB1;
    wire signed [3:0] DOPB1;
    wire [8:0] ADDRB1;
    wire signed [31:0] DIB1;
    wire signed [3:0] DIPB1;
    wire ENB1;
    wire CLKB1;
    wire WEB1;
    wire SSRB1;
    wire signed [31:0] DOA0;
    wire signed [3:0] DOPA0;
    wire [8:0] ADDRA0;
    wire signed [31:0] DIA0;
    wire signed [3:0] DIPA0;
    wire ENA0;
    wire CLKA0;
    wire WEA0;
    wire SSRA0;
    wire signed [31:0] DOB0;
    wire signed [3:0] DOPB0;
    wire [8:0] ADDRB0;
    wire signed [31:0] DIB0;
    wire signed [3:0] DIPB0;
    wire ENB0;
    wire CLKB0;
    wire WEB0;
    wire SSRB0;
    RAMB16_S36_S36 bram1(.DOA(DOA1), .DOPA(DOPA1), .ADDRA(ADDRA1), .DIA(DIA1), .DIPA(DIPA1), .ENA(ENA1), .CLKA(CLKA1), .WEA(WEA1), .SSRA(SSRA1), .DOB(DOB1), .DOPB(DOPB1), .ADDRB(ADDRB1), .DIB(DIB1), .DIPB(DIPB1), .ENB(ENB1), .CLKB(CLKB1), .WEB(WEB1), .SSRB(SSRB1));
    RAMB16_S36_S36 bram0(.DOA(DOA0), .DOPA(DOPA0), .ADDRA(ADDRA0), .DIA(DIA0), .DIPA(DIPA0), .ENA(ENA0), .CLKA(CLKA0), .WEA(WEA0), .SSRA(SSRA0), .DOB(DOB0), .DOPB(DOPB0), .ADDRB(ADDRB0), .DIB(DIB0), .DIPB(DIPB0), .ENB(ENB0), .CLKB(CLKB0), .WEB(WEB0), .SSRB(SSRB0));
    CACHE_BRAM_WRAP wrap(.clk(clk), .din(din), .valid_in(valid_in), .tagi(tagi), .index(index), .offset(offset), .we(we), .en(en), .dout(dout), .tago(tago), .valid(valid), .DOA0(DOA0), .DOB0(DOB0), .DOA1(DOA1), .DOB1(DOB1), .DOPA0(DOPA0), .DOPB0(DOPB0), .DOPA1(DOPA1), .DOPB1(DOPB1), .ADDRA0(ADDRA0), .ADDRB0(ADDRB0), .ADDRA1(ADDRA1), .ADDRB1(ADDRB1), .DIA0(DIA0), .DIB0(DIB0), .DIA1(DIA1), .DIB1(DIB1), .DIPA0(DIPA0), .DIPB0(DIPB0), .DIPA1(DIPA1), .DIPB1(DIPB1), .ENA0(ENA0), .ENB0(ENB0), .ENA1(ENA1), .ENB1(ENB1), .CLKA0(CLKA0), .CLKB0(CLKB0), .CLKA1(CLKA1), .CLKB1(CLKB1), .WEA0(WEA0), .WEB0(WEB0), .WEA1(WEA1), .WEB1(WEB1), .SSRA0(SSRA0), .SSRB0(SSRB0), .SSRA1(SSRA1), .SSRB1(SSRB1));
endmodule