ctrl.v

基于4个mips核的noc设计

module CTRL(enable, en, Opcode, FunctionCode, RegDst, RegValue, Target, Branch, MemRead, MemtoReg, ALUop, MemWrite, ALUSrc, RegWrite, SignExtend, c4, c1, c31);
    input enable;
    wire enable;
    output [0:0] en;
    reg [0:0] en;
    input [5:0] Opcode;
    wire [5:0] Opcode;
    input [5:0] FunctionCode;
    wire [5:0] FunctionCode;
    output [1:0] RegDst;
    reg [1:0] RegDst;
    output [0:0] RegValue;
    reg [0:0] RegValue;
    output [1:0] Target;
    reg [1:0] Target;
    output [1:0] Branch;
    reg [1:0] Branch;
    output [1:0] MemRead;
    reg [1:0] MemRead;
    output [1:0] MemtoReg;
    reg [1:0] MemtoReg;
    output [4:0] ALUop;
    reg [4:0] ALUop;
    output [1:0] MemWrite;
    reg [1:0] MemWrite;
    output [0:0] ALUSrc;
    reg [0:0] ALUSrc;
    output [0:0] RegWrite;
    reg [0:0] RegWrite;
    output [0:0] SignExtend;
    reg [0:0] SignExtend;
    output [31:0] c4;
    reg [31:0] c4;
    output [0:0] c1;
    reg [0:0] c1;
    output [4:0] c31;
    reg [4:0] c31;
    reg [0:0] __tmp61;
    reg [5:0] opcode;
    reg [5:0] functioncode;
    
    always @(Opcode or FunctionCode or enable)
        begin : ctrl_thread
            c4 = 32'b00000000000000000000000000000100;
            c1 = 1'b1;
            c31 = 5'b11111;
            if (enable == 1)
                __tmp61 = 1'b1;
            else
                __tmp61 = 1'b0;
            en = __tmp61;
            RegDst = 2'b00;
            RegValue = 1'b0;
            Target = 2'b00;
            ALUSrc = 1'b0;
            MemtoReg = 2'b00;
            RegWrite = 1'b0;
            MemRead = 2'b00;
            MemWrite = 2'b00;
            Branch = 2'b00;
            ALUop = 5'b00000;
            SignExtend = 1'b0;
            opcode = Opcode;
            functioncode = FunctionCode;
            case (opcode) //synopsys parallel_case
            0:              case (functioncode) //synopsys parallel_case
            8:  begin
                RegDst = 2'b01;
                RegValue = 1'b0;
                Target = 2'b10;
                ALUSrc = 1'b0;
                MemtoReg = 2'b00;
                RegWrite = 1'b0;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b11;
                ALUop = 5'b00010;
                SignExtend = 1'b1;
            end
            9:  begin
                RegDst = 2'b01;
                RegValue = 1'b1;
                Target = 2'b10;
                ALUSrc = 1'b0;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b11;
                ALUop = 5'b00010;
                SignExtend = 1'b1;
            end
            default : begin 
                RegDst = 2'b01;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b0;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b00010;
                SignExtend = 1'b1;
                end
            endcase
            2:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b01;
                ALUSrc = 1'b0;
                MemtoReg = 2'b00;
                RegWrite = 1'b0;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b11;
                ALUop = 5'b00010;
                SignExtend = 1'b1;
            end
            3:  begin
                RegDst = 2'b10;
                RegValue = 1'b1;
                Target = 2'b01;
                ALUSrc = 1'b0;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b11;
                ALUop = 5'b00010;
                SignExtend = 1'b1;
            end
            4:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b0;
                MemtoReg = 2'b00;
                RegWrite = 1'b0;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b01;
                ALUop = 5'b00001;
                SignExtend = 1'b1;
            end
            5:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b0;
                MemtoReg = 2'b00;
                RegWrite = 1'b0;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b10;
                ALUop = 5'b00001;
                SignExtend = 1'b1;
            end
            9:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b00011;
                SignExtend = 1'b1;
            end
            10:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b00111;
                SignExtend = 1'b1;
            end
            11:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b01000;
                SignExtend = 1'b1;
            end
            12:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b00100;
                SignExtend = 1'b0;
            end
            13:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b00101;
                SignExtend = 1'b0;
            end
            14:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b00110;
                SignExtend = 1'b0;
            end
            15:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b1;
                MemRead = 2'b00;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b01001;
                SignExtend = 1'b1;
            end
            32:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b10;
                RegWrite = 1'b1;
                MemRead = 2'b10;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b00000;
                SignExtend = 1'b1;
            end
            35:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b01;
                RegWrite = 1'b1;
                MemRead = 2'b01;
                MemWrite = 2'b00;
                Branch = 2'b00;
                ALUop = 5'b00000;
                SignExtend = 1'b1;
            end
            40:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b0;
                MemRead = 2'b00;
                MemWrite = 2'b10;
                Branch = 2'b00;
                ALUop = 5'b00000;
                SignExtend = 1'b1;
            end
            43:  begin
                RegDst = 2'b00;
                RegValue = 1'b0;
                Target = 2'b00;
                ALUSrc = 1'b1;
                MemtoReg = 2'b00;
                RegWrite = 1'b0;
                MemRead = 2'b00;
                MemWrite = 2'b01;
                Branch = 2'b00;
                ALUop = 5'b00000;
                SignExtend = 1'b1;
            end
            default : begin 
                end
            endcase
        end

endmodule