bram16k_dbgwrapper.v

基于4个mips核的noc设计

module BRAM16K_DBGWRAPPER(DO, ADDR, DI, EN, CLK, WE, RST, dADDR, dDI00, dDI01, dDI02, dDI03, dDI04, dDI05, dDI06, dDI07, dEN, dCLK, dSSR, dWE, dDO00, dDO01, dDO02, dDO03, dDO04, dDO05, dDO06, dDO07);
    output signed  [31:0] DO;
    reg signed [31:0] DO;
    input [31:0] ADDR;
    wire [31:0] ADDR;
    input signed  [31:0] DI;
    wire signed [31:0] DI;
    input EN;
    wire EN;
    input CLK;
    wire CLK;
    input WE;
    wire WE;
    input RST;
    wire RST;
    output [11:0] dADDR;
    reg [11:0] dADDR;
    output signed  [3:0] dDI00;
    reg signed [3:0] dDI00;
    output signed  [3:0] dDI01;
    reg signed [3:0] dDI01;
    output signed  [3:0] dDI02;
    reg signed [3:0] dDI02;
    output signed  [3:0] dDI03;
    reg signed [3:0] dDI03;
    output signed  [3:0] dDI04;
    reg signed [3:0] dDI04;
    output signed  [3:0] dDI05;
    reg signed [3:0] dDI05;
    output signed  [3:0] dDI06;
    reg signed [3:0] dDI06;
    output signed  [3:0] dDI07;
    reg signed [3:0] dDI07;
    output dEN;
    reg dEN;
    output dCLK;
    reg dCLK;
    output dSSR;
    reg dSSR;
    output dWE;
    reg dWE;
    input signed  [3:0] dDO00;
    wire signed [3:0] dDO00;
    input signed  [3:0] dDO01;
    wire signed [3:0] dDO01;
    input signed  [3:0] dDO02;
    wire signed [3:0] dDO02;
    input signed  [3:0] dDO03;
    wire signed [3:0] dDO03;
    input signed  [3:0] dDO04;
    wire signed [3:0] dDO04;
    input signed  [3:0] dDO05;
    wire signed [3:0] dDO05;
    input signed  [3:0] dDO06;
    wire signed [3:0] dDO06;
    input signed  [3:0] dDO07;
    wire signed [3:0] dDO07;
    reg clk;
    reg [11:0] addr;
    reg signed [31:0] dwr;
    reg signed [3:0] dwr0;
    reg signed [3:0] dwr1;
    reg signed [3:0] dwr2;
    reg signed [3:0] dwr3;
    reg signed [3:0] dwr4;
    reg signed [3:0] dwr5;
    reg signed [3:0] dwr6;
    reg signed [3:0] dwr7;
    reg en;
    reg we;
    reg signed [3:0] d0;
    reg signed [3:0] d1;
    reg signed [3:0] d2;
    reg signed [3:0] d3;
    reg signed [3:0] d4;
    reg signed [3:0] d5;
    reg signed [3:0] d6;
    reg signed [3:0] d7;
    reg signed [31:0] data;
    
    always @(ADDR or DI or EN or WE or RST or CLK)
        begin : in
            clk = CLK;
            dCLK = clk;
            addr = ADDR[13:2];
            dADDR = addr;
            dwr = DI;
            dwr0 = dwr[31:28];
            dwr1 = dwr[27:24];
            dwr2 = dwr[23:20];
            dwr3 = dwr[19:16];
            dwr4 = dwr[15:12];
            dwr5 = dwr[11:8];
            dwr6 = dwr[7:4];
            dwr7 = dwr[3:0];
            dDI00 = dwr0;
            dDI01 = dwr1;
            dDI02 = dwr2;
            dDI03 = dwr3;
            dDI04 = dwr4;
            dDI05 = dwr5;
            dDI06 = dwr6;
            dDI07 = dwr7;
            en = EN;
            we = WE;
            dEN = en;
            dWE = we;
            dSSR = 0;
        end

    
    always @(dDO00 or dDO01 or dDO02 or dDO03 or dDO04 or dDO05 or dDO06 or dDO07)
        begin : out
            d0 = dDO00;
            d1 = dDO01;
            d2 = dDO02;
            d3 = dDO03;
            d4 = dDO04;
            d5 = dDO05;
            d6 = dDO06;
            d7 = dDO07;
            data = {d0, d1, d2, d3, d4, d5, d6, d7};
            DO = data;
        end

endmodule