📄 exuart.cod
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; Listing generated by Microsoft (R) Optimizing Compiler Version 13.10.4091
TTL D:\WINCE500\PLATFORM\BERRYDALE\SRC\BOOTLOADER\EBOOT\.\exuart.c
CODE32
00000 AREA |.drectve|, DRECTVE
DCB "-defaultlib:coredll.lib "
DCB "-defaultlib:corelibc.lib "
EXPORT |EXUART_A_BASE_U_VIRTUAL| [ DATA ]
EXPORT |EXUART_B_BASE_U_VIRTUAL| [ DATA ]
EXPORT |v_pMEMC| [ DATA ]
EXPORT |v_pGPIOReg| [ DATA ]
00000 AREA |.data|, DATA
|v_pGPIOReg| DCD 0xa5300000
|v_pMEMC| DCD 0xa4300000
|EXUART_B_BASE_U_VIRTUAL| DCD 0xba500000
|EXUART_A_BASE_U_VIRTUAL| DCD 0xba900000
IMPORT |OALPAtoVA|
; File d:\wince500\platform\berrydale\src\bootloader\eboot\exuart.c
00000 AREA |.text| { |MyWait| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 AREA |.pdata$$MyWait|, PDATA, SELECTION=5, ASSOC=|.text| { |MyWait| } ; comdat associative
|$T37765| DCD |$L37764|
DCD 0x40001201
; Function compile flags: /Ogsy
00000 AREA |.text| { |MyWait| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 |MyWait| PROC
; 15 : {
00000 |$L37764|
00000 e92d4010 stmdb sp!, {r4, lr}
00004 |$M37762|
00004 e1a04000 mov r4, r0
; 16 : volatile UINT32 *TimerOSCRAddress= (volatile UINT32 *) OALPAtoVA((BULVERDE_BASE_REG_PA_OST + 0x10), FALSE);
00008 e59f0034 ldr r0, [pc, #0x34]
0000c e3a01000 mov r1, #0
00010 eb000000 bl OALPAtoVA
; 17 : UINT32 Value, Time;
; 18 :
; 19 : Time = *TimerOSCRAddress;
00014 e5902000 ldr r2, [r0]
; 20 : Value = Time + (microSeconds * 4);
00018 e0821104 add r1, r2, r4, lsl #2
; 21 : if (Value < Time)
0001c e1510002 cmp r1, r2
00020 2a000002 bcs |$L37530|
00024 |$L37527|
; 22 : { // test for wrap.
; 23 : while (Time < *TimerOSCRAddress);
00024 e5903000 ldr r3, [r0]
00028 e1520003 cmp r2, r3
0002c 3afffffc bcc |$L37527|
00030 |$L37530|
; 24 : }
; 25 : while (*TimerOSCRAddress <= Value);
00030 e5903000 ldr r3, [r0]
00034 e1530001 cmp r3, r1
00038 9afffffc bls |$L37530|
; 26 :
; 27 : }
0003c e8bd4010 ldmia sp!, {r4, lr}
00040 e12fff1e bx lr
00044 |$L37767|
00044 40a00010 DCD 0x40a00010
00048 |$M37763|
ENDP ; |MyWait|
EXPORT |ExUart_Initial|
00000 AREA |.text| { |ExUart_Initial| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 AREA |.pdata$$ExUart_Initial|, PDATA, SELECTION=5, ASSOC=|.text| { |ExUart_Initial| } ; comdat associative
|$T37776| DCD |$L37775|
DCD 0x40006f01
; Function compile flags: /Ogsy
00000 AREA |.text| { |ExUart_Initial| }, CODE, ARM, SELECTION=1 ; comdat noduplicate
00000 |ExUart_Initial| PROC
; 30 : {
00000 |$L37775|
00000 e92d40f0 stmdb sp!, {r4 - r7, lr}
00004 |$M37773|
00004 e1a07001 mov r7, r1
00008 e1a05000 mov r5, r0
; 31 : //Init CS1
; 32 : v_pGPIOReg->GAFR0_L &= 0x3FFFFFFF;//GPIO_15,GAFR0_L,bit30,31,alt_f2
0000c e59f61a4 ldr r6, [pc, #0x1A4]
; 33 : v_pGPIOReg->GAFR0_L |= 0x80000000;
; 34 :
; 35 : v_pGPIOReg->GPDR0 |= 0x00008000;//GPIO_15,GPDR0,bit15,output
; 36 :
; 37 : v_pMEMC->msc0 &= 0x0000FFFF;//msc0,CS1
00010 e3a0ecff mov lr, #0xFF, 24
00014 e38ee0ff orr lr, lr, #0xFF
00018 e5962000 ldr r2, [r6]
; 38 : v_pMEMC->msc0 |= CS1_VALUE;
0001c e3a044b9 mov r4, #0xB9, 8
00020 e384473d orr r4, r4, #0x3D, 14
; 39 :
; 40 : //Init CS5
; 41 : v_pGPIOReg->GAFR1_L &= 0xFFFFFFF3;//GPIO_33,GAFR2_U,bit2,3,alt_f2
00024 e5923054 ldr r3, [r2, #0x54]
; 42 : v_pGPIOReg->GAFR1_L |= 0x00000009;
; 43 :
; 44 : v_pGPIOReg->GPDR1 |= 0x00000002;//GPIO_33,GPDR2,bit1,output
; 45 :
; 46 : v_pMEMC->msc2 &= 0x0000FFFF;//msc2,CS5
; 47 : v_pMEMC->msc2 |= CS5_VALUE;
; 48 :
; 49 : /*
; 50 : while(1)
; 51 : {
; 52 :
; 53 : rEXUARTA_LCR = 0x55;
; 54 : MyWait(50);
; 55 : printf("rEXUARTA_LCR = 0x%x. \r\n", rEXUARTA_LCR);
; 56 : MyWait(50);
; 57 : rEXUARTA_LCR = 0xaa;
; 58 : MyWait(50);
; 59 : printf("rEXUARTA_LCR = 0x%x. \r\n", rEXUARTA_LCR);
; 60 : MyWait(50);
; 61 : rEXUARTA_LCR = 0x5a;
; 62 : MyWait(50);
; 63 : printf("rEXUARTA_LCR = 0x%x. \r\n", rEXUARTA_LCR);
; 64 : MyWait(50);
; 65 : rEXUARTA_LCR = 0xa5;
; 66 : MyWait(50);
; 67 : printf("rEXUARTA_LCR = 0x%x. \r\n", rEXUARTA_LCR);
; 68 : MyWait(50);
; 69 :
; 70 : }
; 71 : */
; 72 : MyWait(500);
00028 e3a00f7d mov r0, #0x7D, 30
0002c e3c33103 bic r3, r3, #3, 2
00030 e5823054 str r3, [r2, #0x54]
00034 e5962000 ldr r2, [r6]
00038 e5923054 ldr r3, [r2, #0x54]
0003c e3833102 orr r3, r3, #2, 2
00040 e5823054 str r3, [r2, #0x54]
00044 e5962000 ldr r2, [r6]
00048 e592300c ldr r3, [r2, #0xC]
0004c e3833902 orr r3, r3, #2, 18
00050 e582300c str r3, [r2, #0xC]
00054 e5962004 ldr r2, [r6, #4]
00058 e5923008 ldr r3, [r2, #8]
0005c e003300e and r3, r3, lr
00060 e5823008 str r3, [r2, #8]
00064 e5962004 ldr r2, [r6, #4]
00068 e5923008 ldr r3, [r2, #8]
0006c e1833004 orr r3, r3, r4
00070 e5823008 str r3, [r2, #8]
00074 e5962000 ldr r2, [r6]
00078 e592305c ldr r3, [r2, #0x5C]
0007c e3c3300c bic r3, r3, #0xC
00080 e582305c str r3, [r2, #0x5C]
00084 e5962000 ldr r2, [r6]
00088 e592305c ldr r3, [r2, #0x5C]
0008c e3833009 orr r3, r3, #9
00090 e582305c str r3, [r2, #0x5C]
00094 e5962000 ldr r2, [r6]
00098 e5923010 ldr r3, [r2, #0x10]
0009c e3833002 orr r3, r3, #2
000a0 e5823010 str r3, [r2, #0x10]
000a4 e5962004 ldr r2, [r6, #4]
000a8 e5923010 ldr r3, [r2, #0x10]
000ac e003300e and r3, r3, lr
000b0 e5823010 str r3, [r2, #0x10]
000b4 e5962004 ldr r2, [r6, #4]
000b8 e5923010 ldr r3, [r2, #0x10]
000bc e1833004 orr r3, r3, r4
000c0 e5823010 str r3, [r2, #0x10]
000c4 eb000000 bl MyWait
; 73 :
; 74 : if( uart == 0 ) //ExUartA
000c8 e3550000 cmp r5, #0
000cc 1a00001a bne |$L37537|
; 75 : {
; 76 : /*
; 77 : * Ensuring UART and interrupts are off before configuring
; 78 : * even though LCR and IER reset values are 0x0.
; 79 : */
; 80 : rEXUARTA_LCR = 0x00; // clearing line control register
000d0 e596300c ldr r3, [r6, #0xC]
000d4 e3a02000 mov r2, #0
; 81 : rEXUARTA_IER_DLM = 0x00; // cleareig interrupt control register
; 82 :
; 83 : /*
; 84 : * Set the Baud Rate (Divisor low = DEBUG_BAUD_38400)
; 85 : * Divisor latches are at offsets 0 and 1, which are
; 86 : * receive/transmit data and ier registers.
; 87 : */
; 88 : rEXUARTA_LCR = 0x80; // DLAB=1: access divisor latch register
000d8 e3a01080 mov r1, #0x80
000dc e5832300 str r2, [r3, #0x300]
000e0 e596300c ldr r3, [r6, #0xC]
; 89 : rEXUARTA_RHR_THR_DLL = baud; // divisor latch register's low byte
; 90 : rEXUARTA_IER_DLM = 0x00; // divisor latch register's high byte
; 91 : rEXUARTA_LCR = 0x00; // DLAB=0: not access divisor latch register
; 92 :
; 93 : /* Setting UART properties to 8N1 */
; 94 : rEXUARTA_LCR = 0x03; // 8 bits, 1 stop, no parity. Also LCR's DLAB=0
000e4 e3a00003 mov r0, #3
; 95 : rEXUARTA_ISR_FCR_AFR = 0x01; // enable FIFO of transmit and receive
000e8 e3a04001 mov r4, #1
000ec e5832100 str r2, [r3, #0x100]
000f0 e596300c ldr r3, [r6, #0xC]
; 96 : rEXUARTA_ISR_FCR_AFR = 0x07; // reset FIFO of transmit and recieve
000f4 e3a0e007 mov lr, #7
000f8 e5831300 str r1, [r3, #0x300]
000fc e596300c ldr r3, [r6, #0xC]
00100 e5837000 str r7, [r3]
00104 e596300c ldr r3, [r6, #0xC]
00108 e5832100 str r2, [r3, #0x100]
0010c e596300c ldr r3, [r6, #0xC]
00110 e5832300 str r2, [r3, #0x300]
00114 e596300c ldr r3, [r6, #0xC]
00118 e5830300 str r0, [r3, #0x300]
0011c e596300c ldr r3, [r6, #0xC]
00120 e5834200 str r4, [r3, #0x200]
00124 e596300c ldr r3, [r6, #0xC]
00128 e583e200 str lr, [r3, #0x200]
; 97 :
; 98 : /*
; 99 : * Don't enable UART, place in polled mode.
; 100 : * UART is not enabled till GPIO pins are configured also.
; 101 : * We don't have to configure INTC_REGS to use IRQ and enable interrupt,
; 102 : * as UART is used in polling mode only.
; 103 : */
; 104 : rEXUARTA_IER_DLM = 0x00; // don't need interrupt register in polled mode
0012c e596300c ldr r3, [r6, #0xC]
00130 e5832100 str r2, [r3, #0x100]
; 105 :
; 106 : /*
; 107 : * Ensuring loop back test mode is off
; 108 : * even though MCR reset value is 0x0.
; 109 : */
; 110 : rEXUARTA_MCR = 0x00; // UART is in normal mode,not lookback model.
00134 e596300c ldr r3, [r6, #0xC]
; 111 : }
; 112 : else if( uart == 1 ) //ExUartB
00138 ea00001b b |$L37772|
0013c |$L37537|
0013c e3550001 cmp r5, #1
00140 1a00001a bne |$L37550|
; 113 : {
; 114 : /*
; 115 : * Ensuring UART and interrupts are off before configuring
; 116 : * even though LCR and IER reset values are 0x0.
; 117 : */
; 118 : rEXUARTB_LCR = 0x00; // clearing line control register
00144 e5963008 ldr r3, [r6, #8]
00148 e3a02000 mov r2, #0
; 119 : rEXUARTB_IER_DLM = 0x00; // cleareig interrupt control register
; 120 :
; 121 : /*
; 122 : * Set the Baud Rate (Divisor low = DEBUG_BAUD_38400)
; 123 : * Divisor latches are at offsets 0 and 1, which are
; 124 : * receive/transmit data and ier registers.
; 125 : */
; 126 : rEXUARTB_LCR = 0x80; // DLAB=1: access divisor latch register
0014c e3a01080 mov r1, #0x80
00150 e5832300 str r2, [r3, #0x300]
00154 e5963008 ldr r3, [r6, #8]
; 127 : rEXUARTB_RHR_THR_DLL = baud; // divisor latch register's low byte
; 128 : rEXUARTB_IER_DLM = 0x00; // divisor latch register's high byte
; 129 : rEXUARTB_LCR = 0x00; // DLAB=0: not access divisor latch register
; 130 :
; 131 : /* Setting UART properties to 8N1 */
; 132 : rEXUARTB_LCR = 0x03; // 8 bits, 1 stop, no parity. Also LCR's DLAB=0
00158 e3a00003 mov r0, #3
; 133 : rEXUARTB_ISR_FCR_AFR = 0x01; // enable FIFO of transmit and receive
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