bcddecoder_4_10.tan.rpt

将BCD码的转换为四位二进制,实现是一个十线输入,四线输出的转换功能

Timing Analyzer report for bcddecoder_4_10
Sun Nov 16 20:38:33 2008
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                            ;
+------------------------------+-------+---------------+-------------+-----------+------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From      ; To         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-----------+------------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 5.405 ns    ; datain[4] ; dataout[0] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;           ;            ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-----------+------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM570F256C3       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-----------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To         ;
+-------+-------------------+-----------------+-----------+------------+
; N/A   ; None              ; 5.405 ns        ; datain[4] ; dataout[0] ;
; N/A   ; None              ; 5.254 ns        ; datain[3] ; dataout[0] ;
; N/A   ; None              ; 5.243 ns        ; datain[5] ; dataout[0] ;
; N/A   ; None              ; 5.191 ns        ; datain[2] ; dataout[0] ;
; N/A   ; None              ; 5.151 ns        ; datain[7] ; dataout[0] ;
; N/A   ; None              ; 4.959 ns        ; datain[1] ; dataout[0] ;
; N/A   ; None              ; 4.954 ns        ; datain[6] ; dataout[0] ;
; N/A   ; None              ; 4.940 ns        ; datain[8] ; dataout[0] ;
; N/A   ; None              ; 4.894 ns        ; datain[5] ; dataout[2] ;
; N/A   ; None              ; 4.735 ns        ; datain[4] ; dataout[1] ;
; N/A   ; None              ; 4.702 ns        ; datain[8] ; dataout[2] ;
; N/A   ; None              ; 4.702 ns        ; datain[8] ; dataout[1] ;
; N/A   ; None              ; 4.677 ns        ; datain[5] ; dataout[1] ;
; N/A   ; None              ; 4.657 ns        ; datain[9] ; dataout[0] ;
; N/A   ; None              ; 4.586 ns        ; datain[3] ; dataout[1] ;
; N/A   ; None              ; 4.523 ns        ; datain[2] ; dataout[1] ;
; N/A   ; None              ; 4.310 ns        ; datain[7] ; dataout[2] ;
; N/A   ; None              ; 4.310 ns        ; datain[7] ; dataout[1] ;
; N/A   ; None              ; 4.304 ns        ; datain[4] ; dataout[2] ;
; N/A   ; None              ; 4.232 ns        ; datain[6] ; dataout[2] ;
; N/A   ; None              ; 4.229 ns        ; datain[6] ; dataout[1] ;
; N/A   ; None              ; 4.101 ns        ; datain[8] ; dataout[3] ;
; N/A   ; None              ; 4.082 ns        ; datain[9] ; dataout[2] ;
; N/A   ; None              ; 4.082 ns        ; datain[9] ; dataout[1] ;
; N/A   ; None              ; 3.481 ns        ; datain[9] ; dataout[3] ;
+-------+-------------------+-----------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Nov 16 20:38:33 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bcddecoder_4_10 -c bcddecoder_4_10
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "datain[4]" to destination pin "dataout[0]" is 5.405 ns
    Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_G2; Fanout = 3; PIN Node = 'datain[4]'
    Info: 2: + IC(0.820 ns) + CELL(0.571 ns) = 2.099 ns; Loc. = LC_X1_Y7_N7; Fanout = 1; COMB Node = 'dataout~242'
    Info: 3: + IC(0.191 ns) + CELL(0.125 ns) = 2.415 ns; Loc. = LC_X1_Y7_N8; Fanout = 1; COMB Node = 'dataout~243'
    Info: 4: + IC(0.191 ns) + CELL(0.125 ns) = 2.731 ns; Loc. = LC_X1_Y7_N9; Fanout = 1; COMB Node = 'dataout~244'
    Info: 5: + IC(1.220 ns) + CELL(1.454 ns) = 5.405 ns; Loc. = PIN_N3; Fanout = 0; PIN Node = 'dataout[0]'
    Info: Total cell delay = 2.983 ns ( 55.19 % )
    Info: Total interconnect delay = 2.422 ns ( 44.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Nov 16 20:38:33 2008
    Info: Elapsed time: 00:00:02