dec643.h

自己编写的,采用DSP实现字符叠加的程序,基于合众达SEED-DEC643的扳子,CCS2.2环境,原来的例程是采用FPGA实现字符叠加的,改程序完全采用DSP进行叠加.

/**************************************************************************/
/*  Copyright 2003 by SEED.                                               */
/*  All rights reserved. Property of SEED.                                */
/**************************************************************************/

/*
 *  ======== DEC643.h ========
 *
 *  This file contains DEC643 board initialization and FPGA register access
 *  functions.
 *
 *  DEC643 BSL Version 1.00 - 07/02/2003
 *
 */

#ifndef DEC643_
#define DEC643_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>
#include <csl_i2c.h>
#include <csl_gpio.h>

/*
 *  Note:  Bit definitions for each register field
 *         needs to be supplied here for the CPLD
 *	       and other board periperals.
 */

/* Compatability definitions */
#define NULL                 0

/* CPLD address definitions */
#define DEC643_CPLD_BASE       	0xA0000000
#define DEC643_SDRAM_BASE  		0x80000000

/* CPLD Register Indices */
#define DEC643_CTL_REG    	   0x00 
#define DEC643_UARTCTL_REG     0x01
#define DEC643_INTSTAT_REG	   0x02
#define DEC643_STAT_REG		   0x03
#define DEC643_FLASH_REG       0x04
#define DEC643_WDOG_REG        0x05

/* FPGA definitions */
#define EVMDM642_FPGALEN      0x393d8

/* I2C handle */
extern I2C_Handle DEC643_I2C_hI2C;

/* GPIO handle */
extern GPIO_Handle EVMDM642_GPIO_hGPIO;

/* Read an 8-bit value from a CPLD register */
Uint8 DEC643_rget(Int16 regnum);

/* Write an 8-bit value to a CPLD register */
void DEC643_rset(Int16 regnum, Uint8 regval);

/* Spin in a delay loop for delay iterations */
void DEC643_wait(Uint32 delay);

/* Spin in a delay loop for delay microseconds */
void DEC643_waitusec(Uint32 delay);

/* Send a configuration file to the FPGA */
void DEC642_loadFpga(Uint32 fpgaaddr);

#ifdef __cplusplus
}
#endif

#endif