syslib.c

MPC8360MDS VXWORKS BSP

    
/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/

char * sysModel (void)
    {
    char * model;
    if ((vxPvrGet() & 0xffff0000) == 0x80830000)
	{
	UINT32 temp;
	temp=vxSvrGet();
	switch(temp & 0xffff0000)
	    {
	    case 0x80480000:
		model = SYS_MODEL_8360;
		break;
	    case 0x80500000:
		model = SYS_MODEL_8349E;
		break;
	    case 0x80510000:
		model = SYS_MODEL_8349;
		break;
	    case 0x80520000:
		model = SYS_MODEL_8347ET;
		break;
	    case 0x80530000:
		model = SYS_MODEL_8347T;
		break;
	    case 0x80540000:
		model = SYS_MODEL_8347EP;
		break;
	    case 0x80550000:
		model = SYS_MODEL_8347P;
		break;
	    case 0x80560000:
		model = SYS_MODEL_8343E;
		break;
	    case 0x80570000:
		model = SYS_MODEL_8343;
		break;
	    default:
		model = "Freescale E300 - Unknown version";
		break;
	    }
	}
    else
	{
	model = SYS_MODEL_UNKNOWN;
	}
    return(model);

    }

/*******************************************************************************
* sysBspRev - return the bsp version with the revision eg 1.0/<x>
*
* This function returns a pointer to a bsp version with the revision.
* for eg. 1.0/<x>. BSP_REV defined in config.h is concatanated to
* BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

/******************************************************************************
*
* sysHwMemInit - initialize and configure system memory.
*
* This routine is called before sysHwInit(). It performs memory auto-sizing
* and updates the system's physical regions table, `sysPhysRgnTbl'. It may
* include the code to do runtime configuration of extra memory controllers.
*
* NOTE: This routine should not be called directly by the user application.  It
* cannot be used to initialize interrupt vectors.
*
* RETURNS: N/A
*/

void sysHwMemInit (void)
    {
    /* Call sysPhysMemTop() to do memory autosizing if available */

    sysPhysMemDesc[1].len = (UINT)(sysPhysMemTop () -  RAM_LOW_ADRS);
    

    }


/****************************************************************************
*
* qeIOPortInit - Init values to establish correct IO Port configuration.
*
* The routine sets up the pin connections for the functionality required by 
* this BSP. The information is obtained from the chip users maunual and the 
* board schematics.
*
* RETURNS: NONE
*
* ERROR
*/

void qeIOPortInit()
    {

    /* UCC1 Ethernet */
    qeIOPortSet(QE_PORTA,  1, 3, 0, 2); /* MDIO */
    qeIOPortSet(QE_PORTA,  2, 1, 0, 1); /* MDC */

    qeIOPortSet(QE_PORTA,  0, 2, 0, 1); /* RX_CLK */
    qeIOPortSet(QE_PORTA,  3, 1, 0, 1); /* TxD0 */
    qeIOPortSet(QE_PORTA,  4, 1, 0, 1); /* TxD1 */
    qeIOPortSet(QE_PORTA,  5, 1, 0, 1); /* TxD2 */
    qeIOPortSet(QE_PORTA,  6, 1, 0, 1); /* TxD3 */
    qeIOPortSet(QE_PORTA,  7, 1, 0, 1); /* TX_EN */
    qeIOPortSet(QE_PORTA,  8, 1, 0, 1); /* TX_ER */
    qeIOPortSet(QE_PORTA,  9, 2, 0, 1); /* RxD0 */
    qeIOPortSet(QE_PORTA, 10, 2, 0, 1); /* RxD1 */
    qeIOPortSet(QE_PORTA, 11, 2, 0, 1); /* RxD2 */
    qeIOPortSet(QE_PORTA, 12, 2, 0, 1); /* RxD3 */
    qeIOPortSet(QE_PORTA, 13, 2, 0, 1); /* RxD4 */
    qeIOPortSet(QE_PORTA, 15, 2, 0, 1); /* RX_DV */
    qeIOPortSet(QE_PORTA, 16, 2, 0, 1); /* RX_ER */

    qeIOPortSet(QE_PORTB,  0, 2, 0, 2); /* RxD6 */
    qeIOPortSet(QE_PORTB,  1, 2, 0, 2); /* RxD5 */
    qeIOPortSet(QE_PORTB,  4, 2, 0, 2); /* RxD7 */
    qeIOPortSet(QE_PORTB,  6, 1, 0, 3); /* TxD4 */
    qeIOPortSet(QE_PORTB,  7, 1, 0, 1); /* TxD5 */
    qeIOPortSet(QE_PORTB,  9, 1, 0, 2); /* TxD6 */
    qeIOPortSet(QE_PORTB, 10, 1, 0, 2); /* TxD7 */
    qeIOPortSet(QE_PORTC,  8, 2, 0, 1); /* GTX125 - CLK9 */
    qeIOPortSet(QE_PORTC,  9, 1, 0, 3); /* GTX_CLK - CLK10 */

    
    /* inputs in order : port pin direction opendrain assignment */ 
    qeIOPortSet(QE_PORTA,  17, 1, 0, 1); /* TxD0 */
    qeIOPortSet(QE_PORTA,  18, 1, 0, 1); /* TxD1 */
    qeIOPortSet(QE_PORTA,  19, 1, 0, 1); /* TxD2 */
    qeIOPortSet(QE_PORTA,  20, 1, 0, 1); /* TxD3 */
    qeIOPortSet(QE_PORTA,  21, 1, 0, 1); /* TX_EN */
    qeIOPortSet(QE_PORTA,  22, 1, 0, 1); /* TX_ER */
    qeIOPortSet(QE_PORTA,  23, 2, 0, 1); /* RxD0 */
    qeIOPortSet(QE_PORTA,  24, 2, 0, 1); /* RxD1 */
    qeIOPortSet(QE_PORTA,  25, 2, 0, 1); /* RxD2 */
    qeIOPortSet(QE_PORTA,  26, 2, 0, 1); /* RxD3 */
    qeIOPortSet(QE_PORTA,  27, 2, 0, 1); /* RxD4 */
    qeIOPortSet(QE_PORTA,  28, 2, 0, 1); /* CRS */
    qeIOPortSet(QE_PORTA,  29, 2, 0, 1); /* RX_DV */
    qeIOPortSet(QE_PORTA,  30, 2, 0, 1); /* RX_ER */

    qeIOPortSet(QE_PORTB,  2,  1, 0, 1); /* TxD4 */
    qeIOPortSet(QE_PORTB,  3,  1, 0, 2); /* TxD5 */
    qeIOPortSet(QE_PORTB,  5,  1, 0, 3); /* TxD6 */
    qeIOPortSet(QE_PORTB,  8,  1, 0, 3); /* TxD7 */
    qeIOPortSet(QE_PORTB,  11, 2, 0, 2); /* RxD7 */
    qeIOPortSet(QE_PORTB,  12, 2, 0, 2); /* RxD5 */
    qeIOPortSet(QE_PORTB,  13, 2, 0, 3); /* RxD6 */
   
    qeIOPortSet(QE_PORTC,  2,  1, 0, 2); /* GTX CLK */
    qeIOPortSet(QE_PORTC,  3,  2, 0, 1); /* 125M CLK4*/

    qeIOPortSet(QE_PORTA,  31, 2, 0, 1); /* RX_CLK */

#ifdef INCLUDE_PIB_SUPPORT
#ifdef INCLUDE_PCI

    qeIOPortSet(QE_PORTC,  5, 2, 0, 1); /* CLK6 */
    qeIOPortSet(QE_PORTF,  0, 1, 0, 2); /*  */
    qeIOPortSet(QE_PORTF,  1, 2, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  2, 1, 0, 1); /*  */
    qeIOPortSet(QE_PORTF,  3, 2, 0, 2); /*  */
    qeIOPortSet(QE_PORTF,  4, 2, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  5, 1, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  6, 1, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  7, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  8, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  9, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  10, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  11, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  12, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  13, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  14, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  15, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  16, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  17, 2, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  18, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  19, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  20, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  21, 2, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  22, 2, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  23, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  24, 1, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  25, 1, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  26, 1, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  27, 1, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  28, 1, 0, 3); /*  */
    qeIOPortSet(QE_PORTF,  29, 1, 0, 3); /*  */

    qeIOPortSet(QE_PORTG,  0, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  1, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  2, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  3, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  4, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  5, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  6, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  7, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  8, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  9, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  10, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  11, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  12, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  13, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  14, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  15, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  16, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  17, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  18, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  19, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  20, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  21, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  22, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  23, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  24, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  25, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  26, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  27, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  28, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  29, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  30, 3, 0, 3); /*  */
    qeIOPortSet(QE_PORTG,  31, 3, 0, 3); /*  */

#endif
#endif
    *QE_SDMR(CCSBAR) |=   0x80000000; /* enabling gbl bit for snooping */

    *QE_CMXUCR1(CCSBAR) = 0x00050000;
    *QE_CMXUCR3(CCSBAR) = 0x00060000;
    *QE_CMXUPCR(CCSBAR) = 0x00006000;
    }


/*************************************************************************
*
* qeCpcrReset - Resets Quicc Engine which is required prior to use.
* 
* All of the qe commands after this should be performed via vxBus method.
*
* RETURNS: STATUS
*
* ERROR
*/
STATUS qeCpcrReset()
    {
    UINT32 cpcrValTmp;
    volatile int ix = 0;

    /* wait until the CP is clear */
    do
        {
        cpcrValTmp = *(VUINT32*)(CCSBAR + QUICC_ENGINE_BA + QE_CPCR);

        if (ix++ == QE_CPCR_LATENCY)
            break;
        }
    while (cpcrValTmp & QE_CPCR_FLG) ;

    if (ix >= QE_CPCR_LATENCY)
        {
        return(ERROR);
        }
    
    *(VUINT32*)(CCSBAR  + QUICC_ENGINE_BA +  QE_CPCR) = 0x80010000;

    /* Flush the write pipe */

    CACHE_PIPE_FLUSH ();

    /* wait until the CP is clear */
    ix = 0;

    do
        {
        cpcrValTmp = *(VUINT32*)(CCSBAR  + QUICC_ENGINE_BA + QE_CPCR);

        }
    while (cpcrValTmp & QE_CPCR_FLG) ;
    
    return(OK);
    }

/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes features of the MPC8360-MDS board. It sets up
* the control registers, initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: NA
*/

void sysHwInit (void)
    {

    
#ifdef INCLUDE_PCI
    /* This is a workaround for errata PCI9 */
    *M83XX_ACR(CCSBAR) |= M83XX_ACR_PARKM_PCI;  /* Park on PCI */
    /* This is primarily for PIB PCI support */
    *M83XX_OCCR(CCSBAR) = 0xe0000000; /* PCI_OUTPUT_CLK 0-2 */
#else
    *M83XX_ACR(CCSBAR) &= ~M83XX_ACR_PARKM_PCI; /* Park PPC core */
#endif
    
    /* Initialize Machine check pin */
    vxHid0Set(0x80000000);
    vxMsrSet(vxMsrGet()|0x00000002);

    *BCSR10 = 0; /* Unprotect flash - set gmii mode */

    /* HID2 [IFEB / IFEC / EBQS / EBPX] See MPC8349 for details */
    /* This will make use of under the hood architecture features */
    vxHid2Set(vxHid2Get()|0x04e00000);

    /* set pointer to BAT initialization functions */
    _pSysBatInitFunc = (FUNCPTR) mmuPpcBatInitMPC7x5;


    /* Enable the e300 core timebase */
    *M83XX_SPCR(CCSBAR) |= M83XX_SPCR_TBEN;

#ifdef INCLUDE_VXBUS
    /* initialize local bus methods here */
    plbMethodInit();
#endif

#ifdef INCLUDE_VXBUS
    hardWareInterFaceInit();
#endif /* INCLUDE_VXBUS */


#ifndef DRV_SIO_NS16550
    sysDuartHwInit();
#endif

    /* put correct memory size in sysPhysMemDesc[1].len for
     * size of local memory
     */
    sysHwMemInit();

    /* set the TSEC/SEC/USB/PCI 1-1 enabled clocking with CSB */
    /* Do we need to set these and if so in romInit.s */

    CACHE_PIPE_FLUSH();

    /* Get the Baud Rate Generator Clock  frequency */

    baudRateGenClk = sysBaudClkFreq();

/* ifdef PIB, setup PIB */

#ifdef INCLUDE_PIB_SUPPORT
    i2cDrvInit(0,0);
    i2cDrvInit(1,0);    
    initPibBoard();
#endif

    /* Initialize interrupts */
    mds8360IntrInit(); /* Enable dual interrupt controller access*/

#ifdef REV1_1_SILICON
    /* Check revision anyway */
    if((vxSvrGet() & 0xffff) == 0x11)
	loadEnet15Patch();
#endif

    quiccIntrInit(); /* Standard 834x controller */

    qeIntrInit(); /* Quicc Engine Interrupt controller */

    qeIOPortInit();

    while(qeCpcrReset()!=OK);

#ifdef INCLUDE_SECURITY_ENGINE
    /* Initialize the Security Block */
    *QUICC_SECMR (CCSBAR) = 0xfffe0000;    
    *QUICC_SECBR (CCSBAR) = SEC_ENG_BASE_ADRS | 0x1;

#endif 

#ifdef INCLUDE_PCI
    /* config pci */
    if (pciConfigLibInit (PCI_MECHANISM_0,(ULONG) sysPciConfigRead,
			  (ULONG) sysPciConfigWrite,(ULONG) sysPciSpecialCycle) != OK)
        {
        sysToMonitor (BOOT_NO_AUTOBOOT);  /* BAIL */
        }

    /*  Initialize PCI interrupt library. */

    if ((pciIntLibInit ()) != OK)
        {
        sysToMonitor (BOOT_NO_AUTOBOOT);
        }

    mot83xxBridgeInit();

#ifdef INCLUDE_PCI_AUTOCONF
    sysPciAutoConfig();
#endif /* INCLUDE_PCI_AUTOCONF */

#endif /* INCLUDE_PCI */

    /*
     * The power management mode is initialized here. Reduced power mode
     * is activated only when the kernel is idle (cf vxPowerDown).
     * Power management mode is selected via vxPowerModeSet().
     * DEFAULT_POWER_MGT_MODE is defined in config.h.
     */

    vxPowerModeSet (DEFAULT_POWER_MGT_MODE);

    }


/***************************************************************************
*
* sysGetPeripheralBase   - Provides CCSRBAR address fro security engine 
*                          drivers.
*
* RETURNS:
*
* ERRNO
*/
UINT32 sysGetPeripheralBase()
    {
    return(CCSBAR);
    }


uint32_t sysBaudClkFreq(void)
    {
    /* Temp until better solution found */
    return(sysClkFreqGet());
    }

    /* Temp base freq until better solution found */
UINT32 csb = 0,lbiu,ddr,spmf,clkDiv,corePll,coreFreq = 0,tempVal;


UINT32 sysClkFreqGet()
    {
    int loop;

    /* Read dip switches*/
    tempVal = *M83XX_SPMR(CCSBAR);
    lbiu = M83XX_SPMR_LBIU_VAL(tempVal);
    ddr = M83XX_SPMR_DDR_VAL(tempVal);
    spmf = M83XX_SPMR_SPMF_VAL(tempVal);
    clkDiv = M83XX_SPMR_CLK_DIV(tempVal);
    corePll = M83XX_SPMR_CLK_PLL(tempVal);
    
    /* Assume 66MHz oscillator clk */
    for (loop=0;  clkConfTable[loop].spmf != 0; loop++)
	{
	if(spmf == clkConfTable[loop].spmf)
	    {
	    if (corePll == clkConfTable[loop].corepll)
		{
		coreFreq = clkConfTable[loop].corefreq;
		csb = clkConfTable[loop].csbfreq;
		break;
		}
	    }
	}

    /* If loop drops out the bottom then use default BSP value for CSB */
    if(clkConfTable[loop].spmf == 0)
	{
	csb = SYS_CLK_FREQ;
	coreFreq = csb * (corePll & 3);
	}
    else
	{
	csb = csb * 1000000;
	coreFreq = coreFreq * 1000000;
	}

    return(csb);

    }

/*******************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* Determine installed memory by reading memory control registers
* and calculating if one or 2 chip selects are used for SDRAM.
* Use the address mask and valid bit to determine each bank size.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/

char * sysPhysMemTop (void)
    {
    LOCAL char * physTop = NULL;

    physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);

    return (physTop) ;
    }

/*******************************************************************************
*
* sysMemTop - get the address of the top of VxWorks memory
*
* This routine returns a pointer to the first byte of memory not
* controlled or used by VxWorks.
*
* The user can reserve memory space by defining the macro USER_RESERVED_MEM
* in config.h.  This routine returns the address of the reserved memory
* area.  The value of USER_RESERVED_MEM is in bytes.
*
* RETURNS: The address of the top of VxWorks memory.
*/

char * sysMemTop (void)
    {

    if (memTop == NULL)
        {
        memTop = sysPhysMemTop () - USER_RESERVED_MEM;

#ifdef INCLUDE_EDR_PM

        /* account for ED&R persistent memory */

        memTop = memTop - PM_RESERVED_MEM;
#endif
        }

    return memTop;
    }


/******************************************************************************
*
* sysToMonitor - transfer control to the ROM monitor
*
* This routine transfers control to the ROM monitor.  Normally, it is called
* only by reboot()--which services ^X--and bus errors at interrupt level.
* However, in some circumstances, the user may wish to introduce a
* <startType> to enable special boot ROM facilities.
*
* RETURNS: Does not return.
*/

STATUS sysToMonitor
    (
     int startType	/* parameter passed to ROM to tell it how to boot */
    )
    {
    FUNCPTR pRom = (FUNCPTR) (ROM_TEXT_ADRS + 8);	/* Warm reboot */