syslib.c

MPC8360MDS VXWORKS BSP

/* sysLib.c - Freescale mds8360 board system-dependent library */

/* Copyright (c) 2006 Wind River Systems, Inc. */

/*
modification history
--------------------
01d,25aug06,dtr  WIND00061424 - CPU 1 errata causes intermittent crash.
01c,04aug06,dtr  Allocate static memory for pSysPlbMethods as hwMemAlloc not
                 yet available.
01b,07jun06,dtr  Correct IOPort setting for PIB and set OCCR.
01a 16mar06,dtr  Created form ads834x/sysLib.c
*/

/*
DESCRIPTION

This library provides board-specific routines.

*/

/* includes */

#include <vxWorks.h>
#include <vme.h>
#include <memLib.h>
#include <cacheLib.h>
#include <sysLib.h>
#include "config.h"
#include <string.h>
#include <intLib.h>
#include <logLib.h>
#include <stdio.h>
#include <taskLib.h>
#include <vxLib.h>
#include <tyLib.h>
#include <arch/ppc/mmu603Lib.h>
#include <arch/ppc/vxPpcLib.h>
#include <private/vmLibP.h>

#include <miiLib.h>

#ifdef INCLUDE_PCI
#    include <drv/pci/pciConfigLib.h>
#    include <drv/pci/pciIntLib.h>
#endif /* INCLUDE_PCI */

#ifdef INCLUDE_QE_FCC_HEND
#include <hwif/util/hwMemLib.h>
#include <../src/hwif/h/hEnd/qeFccHEnd.h>
#endif

/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT + _MMU_NUM_EXTRA_IBAT + _MMU_NUM_EXTRA_DBAT)] =
    {
    /* I BAT 0 */
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_32M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    /* use for internal registers into data space */
    /* NOTE! the internal space cannot be cached and should be guarded */
    ((CCSBAR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CCSBAR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 2 - PCI 1 */


    ((0x80000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0x80000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
     _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 4 - PCI 2 */

    ((0x90000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0x90000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
     _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /*
     * These entries are for the I/D BATs (4-7) on the MPC7455/755/834x/8272.
     * They should be defined in the following order.
     * IBAT4U,IBAT4L,IBAT5U,IBAT5L,IBAT6U,IBAT6L,IBAT7U,IBAT7L,
     * DBAT4U,DBAT4L,DBAT5U,DBAT5L,DBAT6U,DBAT6L,DBAT7U,DBAT7L,
     */

    /* I BAT 4 */

    ((LOCAL_MEM_LOCAL_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((LOCAL_MEM_LOCAL_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_MEM_COHERENT),


    /* I BAT 5 */

    0, 0,

    /* I BAT 6 */

    0, 0,

    /* I BAT 7 */

    0, 0,

    /* D BAT 4 */

    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_32M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 5 */

    0, 0,

    /* D BAT 6 */

    0, 0,

    /* D BAT 7 */

    0, 0

 
    };

/*
 * mmuPcpBatInitMPC7x5 initializes the standard 4 (0-3) I/D BATs &
 * the additional 4 (4-7) I/D BATs present on the MPC74[45]5 & MPC83xx.
 */

IMPORT void mmuPpcBatInitMPC7x5(UINT32 *pSysBatDesc); /* MPC7x5 and 83xx BAT Support */
IMPORT FUNCPTR _pSysBatInitFunc;

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, the Board Control and
 * Status registers, the MPC834X Internal Memory Map, and local FLASH RAM are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {

    {
    /* Vector Table and Interrupt Stack */
    (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS,
    (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_GUARDED |
    VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_GUARDED |
    VM_STATE_CACHEABLE_NOT
    },

    {

    (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS + RAM_LOW_ADRS,
    (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS + RAM_LOW_ADRS,
    LOCAL_MEM_SIZE - RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      |
    VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
    },

#ifdef INCLUDE_SECONDARY_DRAM
    {
    (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS2,
    (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS2,
    LOCAL_MEM_SIZE2,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      |
    VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
    },
#endif

    {
    /* Board Control and Status Registers */

    (VIRT_ADDR) BCSR_BASE_ADRS,
    (PHYS_ADDR) BCSR_BASE_ADRS,
    BCSRS_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    }

    ,
    {
    /* MPC834x Device Memory Map */

    (VIRT_ADDR) CCSBAR,
    (PHYS_ADDR) CCSBAR,
    CCSBAR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    }


    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int   sysBus      = BUS;                /* system bus type (VME_BUS, etc) */
int   sysCpu      = CPU;                /* system CPU type (PPC603) */
char *sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char *sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int   sysProcNum;			/* processor number of this CPU */
int   sysFlags;				/* boot flags */
char  sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
BOOL  sysVmeEnable = FALSE;		/* by default no VME */
UINT32   baudRateGenClk;



/* forward declarations */

uint32_t sysDecGet(void);
uint32_t sysBaudClkFreq(void);
UINT32 sysClkFreqGet();
void sysControlLED(int LED,BOOL on);

#ifdef INCLUDE_PCI
STATUS sysPciSpecialCycle (int busNo, UINT32 message);
STATUS sysPciConfigRead   (int busNo, int deviceNo, int funcNo,
			         int offset, int width, void * pData);
STATUS sysPciConfigWrite  (int busNo, int deviceNo, int funcNo,
			         int offset, int width, ULONG data);

void   sysPciConfigEnable (int);

ULONG sysPciConfAddr = (PCI_CFG_ADR_REG);          /* PCI Configuration Address */
ULONG sysPciConfData = (PCI_CFG_ADR_REG);          /* PCI Configuration Data */


#include <pci/pciIntLib.c>           /* PCI int support */
#include <pci/pciConfigLib.c>        /* pci configuration library */

/* use show routine */
#ifdef INCLUDE_SHOW_ROUTINES
#include <pci/pciConfigShow.c>       /* pci configuration show routines */
#endif

/* use pci auto config */

#include <pci/pciAutoConfigLib.c>    /* automatic PCI configuration */
#include "sysBusPci.c"              /* pciAutoConfig BSP support file */
#include "mot83xxPci.c"

#ifdef INCLUDE_GEI8254X_END
LOCAL int   sysPci1SysNum  = PCI_1_BUS;
#ifdef  INCLUDE_SECONDARY_PCI
LOCAL int   sysPci2SysNum  = PCI_2_BUS;
#endif /* INCLUDE_SECONDARY_PCI */
#endif /* INCLUDE_GEI8254X_END */

#endif /* INCLUDE_PCI */


#include "sysDuart.c"

#include <intrCtl/quiccIntrCtl.c>
#include <intrCtl/qeIntrCtl.c>
#include "mds8360IntrMux.c"

#include <timer/quiccTimer.c>

#ifdef INCLUDE_FLASH
#include <mem/flashMem.c>
#include <mem/nvRamToFlash.c>
#else
#include <mem/nullNvRam.c>
#endif

#ifdef INCLUDE_PIB_SUPPORT
#include "sysMotI2c.c"
#include "sysMpc834xI2c.c"
#endif

#include "cmdLine.c"

#ifdef INCLUDE_VXBUS
IMPORT void hardWareInterFaceInit();
#include <vxBusLib.h>
#include <hwif/vxbus/vxBus.h>
#include <../src/hwif/h/resource/qeCp.h>
#include <../src/hwif/h/resource/qeIOPort.h>
#include "hwconf.c"
#ifdef INCLUDE_SIO_UTILS
IMPORT void sysSerialConnectAll(void);
#endif

#endif

void sysLedInit(void);
/* defines */

#define ZERO    0
#define SYS_MODEL_8349  "Freescale MPC8349 ADS"
#define SYS_MODEL_8349E "Freescale MPC8349E ADS"
#define SYS_MODEL_8347T  "Freescale MPC8347 TBGA ADS"
#define SYS_MODEL_8347ET  "Freescale MPC8347E TBGA ADS"
#define SYS_MODEL_8347P  "Freescale MPC8347 PBGA ADS"
#define SYS_MODEL_8347EP  "Freescale MPC8347E PBGA ADS"
#define SYS_MODEL_8343E "Freescale MPC8343E ADS"
#define SYS_MODEL_8343 "Freescale MPC8343 ADS"
#define SYS_MODEL_8360 "Freescale MPC8360 MDS"

#define SYS_MODEL_UNKNOWN "Not an E300 core - device unknown"

/* Set ACR to park on PCI bus */
#define M83XX_ACR_PARKM_PCI 0x1

#ifdef INCLUDE_FEI_END
#   include "sysFei82557End.c"
#endif /* INCLUDE_FEI_END */

#include "sysNet.c"

#ifdef INCLUDE_GEI8254X_END
#include "sysGei82543End.c"
#endif

#ifdef REV1_1_SILICON
#include "qePatch.c"
#endif

/* Clock configuration */
typedef struct 
    {
    UINT32 spmf;
    UINT32 corepll;
    UINT32 clkin;
    UINT32 csbfreq;
    UINT32 corefreq;
    } CLK_TABLE;


LOCAL CLK_TABLE clkConfTable[] = 
    {
#ifdef GNU_SUPPORTS_BINARY_FORMAT
    {0b101 ,0b0000010,66 ,333 ,333},
    {0b101 ,0b0100010,66 ,333 ,333},
    {0b011 ,0b0000100,66 ,200 ,400},
    {0b011 ,0b0100100,66 ,200 ,400},
    {0b100 ,0b0000011,66 ,266 ,400},
    {0b100 ,0b0100011,66 ,266 ,400},
    {0b101 ,0b0000011,66 ,333 ,500},
    {0b101 ,0b0100011,66 ,333 ,500},
    {0b011 ,0b0000101,66 ,200 ,500},
    {0b100 ,0b0000100,66 ,266 ,533},
    {0b011 ,0b0000100,66 ,200 ,600},
    {0b100 ,0b0000101,66 ,266 ,667},
    {0b101 ,0b0000100,66 ,333 ,667},
#else
    {0x5 ,0x02,66 ,333 ,333},
    {0x5 ,0x22,66 ,333 ,333},
    {0x3 ,0x04,66 ,200 ,400},
    {0x3 ,0x24,66 ,200 ,400},
    {0x4 ,0x03,66 ,266 ,400},
    {0x4 ,0x23,66 ,266 ,400},
    {0x5 ,0x03,66 ,333 ,500},
    {0x5 ,0x23,66 ,333 ,500},
    {0x3 ,0x05,66 ,200 ,500},
    {0x4 ,0x04,66 ,266 ,533},
    {0x3 ,0x04,66 ,200 ,600},
    {0x4 ,0x05,66 ,266 ,667},
    {0x5 ,0x04,66 ,333 ,667},    
#endif
    {0}
    };

LOCAL char * memTop = NULL;
LOCAL BOOL configured = FALSE;

#ifdef INCLUDE_VXBUS
IMPORT struct vxbDeviceMethod * pSysPlbMethods;

#define MAX_NUM_METHODS 2


VXB_DRIVER_METHOD_DECL(miiConnectionModify);
STATUS miiConnectionModify(VXB_DEVICE_ID pDev,VXB_DEVICE_ID pInst,void *pArg);
char pSysPlbMethodsMem[(sizeof(struct vxbDeviceMethod *))*MAX_NUM_METHODS];

/*****************************************************************************
*
* plbMethodInit - init methods for processor local bus
* 
* Must install any methods from BSP here so drivers can call them
*
* RETURNS: NONE
*
* ERROR
*/
void plbMethodInit()
    {
    pSysPlbMethods = (struct vxbDeviceMethod *)&pSysPlbMethodsMem[0];
    pSysPlbMethods[0].devMethodId = (UINT32)(&miiConnectionModify_desc[0]);
    pSysPlbMethods[0].handler = (FUNCPTR)miiConnectionModify;
    pSysPlbMethods[1].devMethodId = (0);
    pSysPlbMethods[1].handler = NULL;
    }


/**************************************************************************
* 
* gmii - sets the BCSR reg to gmii mode for the specific unit
*
* RETURNS : NONE
* 
* ERROR
*/
 
void gmii(unitNumber)
    {
    volatile UINT8 bcsrVal=0;

    bcsrVal =  *BCSR10;

    if(unitNumber ==0)
	{
	bcsrVal &= 0x3f;
	bcsrVal |=0x80;
	}
    else
	{
	bcsrVal &= 0xcf;
	bcsrVal |=0x20;
	}	

    *BCSR10 = bcsrVal;
    
    }

/**************************************************************************
* 
* rgmii - sets the BCSR reg to rgmii mode for the specific unit
*
* RETURNS : NONE
* 
* ERROR
*/
void rgmii(unitNumber)
    {
    volatile UINT8 bcsrVal=0;

    bcsrVal =  *BCSR10;

    if(unitNumber ==0)
	{
	bcsrVal &= 0x3f;
	}
    else
	{
	bcsrVal &= 0xcf;
	}	
    
    *BCSR10 = bcsrVal;
    }

#ifdef INCLUDE_QE_FCC_HEND
/*********************************************************************
*  
* miiConnectionModify - method for qefcc driver to update phy
*
* 
*/

STATUS miiConnectionModify(VXB_DEVICE_ID pDev,VXB_DEVICE_ID pInst,void *pArg)
    {
    QE_FCC_MII_PHY_INFO  * pQeFccMiiPhyInfo = (QE_FCC_MII_PHY_INFO  * )pArg;

    if(strcmp(pDev->pName,"qefccHEnd")==0)
	{
	if(pQeFccMiiPhyInfo->speed == 1000000000)
	    {
	    gmii(pQeFccMiiPhyInfo->unit);
	    pQeFccMiiPhyInfo->connectionType = QE_FCC_GMII;
	    }
	else
	    {
	    rgmii(pQeFccMiiPhyInfo->unit);
	    pQeFccMiiPhyInfo->connectionType = QE_FCC_RGMII;
	    }
	}

    return(OK);
    }
#endif /* INCLUDE_QE_FCC_HEND */
#endif /* INCLUDE_VXBUS */