rominit.s

MPC8360MDS VXWORKS BSP

	andi.	r7,r7,0x3FFF   		/* Clear DCE and ICE bits */
	mtspr	HID0,r7
        isync
	sync				/* synchronize */


	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,2), (BCSR_BASE_ADRS))

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,2), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_32KB ))
	
	WRITEADR(r6,r7,QUICC_OR1 (CCSBAR), \
		 0xffffe9f7)

	/* load BR2 */
	WRITEADR(r6,r7,QUICC_BR1 (CCSBAR), \
		 (BCSR_BASE_ADRS & 0xffff0000) | \
		 0x801)

	isync
	sync
	/* Make sure flash unprotected */	
	lis	r6, HIADJ (BCSR10)	
	lbz	r5, LO(BCSR10)(r6)	
	andi.   r5, r5, 0xfb
	stb     r5, LO(BCSR10)(r6)
	
#ifdef INCLUDE_DDR_SDRAM
	/* Memory mapped region base address */
	
	WRITEADR(r6,r7,M83XX_DDRLAWBARn(CCSBAR,0), \
		 DDR_SDRAM_LOCAL_ADRS)
	 
	WRITEADR(r6,r7,M83XX_DDRLAWARn(CCSBAR,0), \
		 LAWAR_ENABLE  | LAWAR_SIZE_256MB ) 

	nop
	nop
	nop
	nop
	isync
		
		
	/* Initialize the DDR Memory controller */
        lis	r6, HI(DDRBA)
        ori	r6, r6, LO(DDRBA)		/* r6 = DDR base */
	WRITEOFFSET(r6,r7,0xf00, 0x202c0000)   /* CAS latency 2.5 Assumed */
	WRITEOFFSET(r6,r7,(CS0_BNDS), 0x00000007)
	WRITEOFFSET(r6,r7,(CS1_BNDS), 0x0008000f)
	WRITEOFFSET(r6,r7,(CS2_BNDS), 0x00000000)
	WRITEOFFSET(r6,r7,(CS3_BNDS), 0x00000000)
	WRITEOFFSET(r6,r7,(CS0_CONFIG), 0x80000101)
	WRITEOFFSET(r6,r7,(CS1_CONFIG), 0x80000101)
	WRITEOFFSET(r6,r7,(CS2_CONFIG), 0x00000101)
	WRITEOFFSET(r6,r7,(CS3_CONFIG), 0x00000101)
	
	WRITEOFFSET(r6,r7,(TIMING_CFG_1), 0x36332321)
	WRITEOFFSET(r6,r7,(TIMING_CFG_2), 0x00000800)
#ifdef USE_32BIT_DDR
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0x420c8000)
#else
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0x42008000)
#endif
	WRITEOFFSET(r6,r7,(DDR_SDRAM_MODE_CFG), 0x00000022)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_INTERVAL), 0x04060100)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CLK_CNTRL), 0x82000000)
	lis  r7,0x0004
	mtctr r7
delayddr1:
	nop
	bdnz delayddr1
#ifdef USE_32BIT_DDR
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0xc20c8000)
#else
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0xc2008000)
#endif	
	
	sync
	isync
	
	

#ifdef INCLUDE_ECC
	WRITEOFFSET(r6,r7,(DDR_ERR_DISABLE), 0x00000000)
	WRITEOFFSET(r6,r7,(DDR_ERR_SBE), 0x00ff0000)
	isync
	sync
	lis     r7, 0x1
	mtspr   9,  r7
eccDelayLoop:
	nop
	bdnz    eccDelayLoop
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0xe2000000)
#endif
	isync
	
#endif /* INCLUDE_DDR_SDRAM */

#ifdef INCLUDE_LBC_SDRAM
	/* Initialise SDRAM */
SdramInit:
	/* Memory mapped region base address */
	
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,1), (LBC_SDRAM_LOCAL_ADRS))

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,1), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_64MB ))
	
	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,1))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,1))
	lwz  r7,0(r6)
        isync
 
	/* load OR2 */

	WRITEADR(r6,r7,QUICC_OR2 (CCSBAR), \
		 (LBC_SDRAM_LOCAL_SIZE_MASK & 0xffff0000) | 0x6901)

	/* load BR2 */
	WRITEADR(r6,r7,QUICC_BR2 (CCSBAR), \
		 (LBC_SDRAM_LOCAL_ADRS & 0xffff0000) | \
		 0x1861)

	/* Pre-charge all banks */
	WRITEADR(r6,r7,QUICC_LSDMR(CCSBAR),0x2862D733 )
 
	lis     r9,HIADJ(LBC_SDRAM_LOCAL_ADRS)
        addi    r9, r9, LO(LBC_SDRAM_LOCAL_ADRS)
 
	/* do a single write to an arbitrary location */

	addi    r5,0,0x00FF      /* Load 0x000000FF into r5 */
	stb     r5,0(r9)         /* Write 0xFF to SDRAM address - bits [24-31] */
	isync
	/* issue a "Auto Refresh" command to SDRAM */

	WRITEADR(r6,r7,QUICC_LSDMR(CCSBAR),0x0862D733)
 
	/* do a single write to an arbitrary location */

	addi    r5,0,0x00FF      /* Load 0x000000FF into r5 */
	stb     r5,0(r9)         /* Write 0xFF to SDRAM address - bits [24-31] */
	isync
	/* issue a "Auto Refresh" command to SDRAM */

	WRITEADR(r6,r7,QUICC_LSDMR(CCSBAR),0x0862D733)
 
	/* do a single write to an arbitrary location */

	addi    r8,0,0x00FF      /* Load 0x000000FF into r8 */

	stb     r8,0(r9)         /* Write 0xFF to address R9  */
	stb     r8,1(r9)         /* Write 0xFF to address R9  */
	stb     r8,2(r9)         /* Write 0xFF to address R9  */
	stb     r8,3(r9)         /* Write 0xFF to address R9  */
	stb     r8,4(r9)         /* Write 0xFF to address R9  */
	stb     r8,5(r9)         /* Write 0xFF to address R9  */
	stb     r8,6(r9)         /* Write 0xFF to address R9  */
	stb     r8,7(r9)         /* Write 0xFF to address R9  */
	
	/* issue a "Mode Register Write" command to SDRAM */

	WRITEADR(r6,r7,QUICC_LSDMR(CCSBAR),0x1862D733)
 
	/* do a single write to an arbitrary location */

	addi    r8,0,0x00FF      /* Load 0x000000FF into r8 */
	stb     r8,0(r9)         /* Write 0xFF to address R9 - bits [24-31] */

	/* enable refresh services and put SDRAM into normal operation  */
	
	WRITEADR(r6,r7,QUICC_LSDMR(CCSBAR),0x4062D733)

	/* program the MRTPR */
	addi    r5,0,TPR  /* MRTPR[TPR] */
        lis     r6, HIADJ (QUICC_MRTPR (CCSBAR))
        addi    r6, r6, LO (QUICC_MRTPR (CCSBAR))
	sth     r5, 0x0 (r6)      /* store upper half-word */

	/* program the LSRT */

	addi    r5,0,LSRT_VALUE
        lis     r6, HIADJ (QUICC_LSRT (CCSBAR))
        addi    r6, r6, LO (QUICC_LSRT (CCSBAR))
	stb     r5, 0x0 (r6)      /* store byte - bits[24-31] */

	isync
	

	lis     r9, HI(LBC_SDRAM_LOCAL_ADRS)
	ori     r9,r9, LO(LBC_SDRAM_LOCAL_ADRS)

	lis	r7, HIADJ(0x100)      /* Loop 256 times */
	addi    r7, r7, LO(0x100)
	mtspr	9,r7             /* Load spr CTR with 8 */
	lis 	r8,0x5555      /* Load 0x000000FF into r8 */
        ori     r8,r8,0x5555


SdramWrLoop2:
	
	stw  	r8,0(r9)        	/* Write 0xFF to address R9 */
	addi    r9,r9,4                 /* Move R9 to next byte */
	addi    r8,r8,1                 /* Add 1 to r8 */
	bc   	16,0,SdramWrLoop2	/* Decrement CTR, and possibly branch */
#endif  /* INCLUDE_LBC_SDRAM */

	WRITEADR(r6,r7, M83XX_PCILAWBARn(CCSBAR,0),0x80000000)
	WRITEADR(r6,r7, M83XX_PCILAWBARn(CCSBAR,1),0x90000000)	
	WRITEADR(r6,r7, M83XX_PCILAWARn(CCSBAR,0),0x8000001b)
	WRITEADR(r6,r7, M83XX_PCILAWARn(CCSBAR,1),0x8000001b)	

	
warm:
	
#ifdef INCLUDE_PCI
        /* Set the pciAutoconfig check to FALSE */
	xor     r5,r5,r5                /* Zero r5 */
	lis     r6,HIADJ(PCI_AUTO_CONFIG_ADRS)                   
	addi	r6,r6,LO(PCI_AUTO_CONFIG_ADRS)
	stw     r5,0(r6)
#endif /* INCLUDE_PCI */
	

	
#if 0
	lis	r6, HIADJ (BCSR1)	/* Make sure flash unprotected */
	lbz	r5, LO(BCSR1)(r6)	
	ori     r5, r5, BCSR1_FLASH_PRT
	stb     r5, LO(BCSR1)(r6)
	
	lis	r6, HIADJ (BCSR0)	/* Make sure flash unprotected */
	lbz	r5, LO(BCSR0)(r6)	
	ori     r5, r5, LO(~BCSR0_SIGNAL1)
	stb     r5, LO(BCSR0)(r6)
#endif
	
	/* turn the instruction cache ON for faster FLASH ROM boots */
	mfspr   r4, HID0
	ori	r4, r4, _PPC_HID0_ICE | _PPC_HID0_ICFI	/* set ICE & ICFI */
	rlwinm	r5, r4, 0, _PPC_HID0_BIT_ICFI + 1, _PPC_HID0_BIT_ICFI - 1

					/* clear the ICFI bit */
	isync

	/*
	 * The setting of the instruction cache enable (ICE) bit must be
	 * preceded by an isync instruction to prevent the cache from being
	 * enabled or disabled while an instruction access is in progress.
	 */

	mtspr	HID0, r4	/* Enable Instr Cache & Inval cache */
	sync
	mtspr	HID0, r5	/* using 2 consec instructions */
				/* E300 core recommendation */
        isync                                

	
	/* 
	Modifying ACR to increase pipeline depth, must retain 
	rsvd bits values. Need to allow for Errata ARB3
	*/
	li      r5, 0x100
	mtctr   r5
	lis     r4, HI(CCSBAR)
	ori     r4, r4, LO(CCSBAR)
        lwz     r5, M83XX_ACR(0)(r4)	
        lis     r6, 0x0003
	ori     r6, r6, 0x0300
	or      r5, r5, r6
	b       iCacheLineLoad /* instruction cache line load */
	.balign 32
loadACR:	
        stw     r5, M83XX_ACR(0)(r4)
	isync
delay:	/* loop idle in cache while ACR update completes */
	nop	
	bdnz  delay
	b continueBoot
iCacheLineLoad:	
	b loadACR

continueBoot:	
        /* initialize the stack pointer */

	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)
	
	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)
 
        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)
 
        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	sub	r6, r6, r7		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */

	mtspr	LR, r6				/* save destination address*/
						/* into LR register */
	blr				/* jump to the C entry point */