rominit.s

MPC8360MDS VXWORKS BSP

/* romInit.s - Motorola mds8360 ROM initialization module */

/* Copyright (c) 2006 Wind River Systems, Inc. */

/*
modification history
--------------------
01e,16oct06,dtr  Fix 60694 - HID0 may be initialized incorrectly.
01d,24aug05,dtr  ARB1 errata still partial fix reqd for rev1.1 silcon.
01c,11aug05,dtr  Provide switch for 32bit DDR.
                 Performance improvement via ACR increase pipeline depth
	         Update for errata with ACR.
01b,16may05,dtr  Memory controller setting for BCSR mod. SPR 108220.
01a,19jan05,dtr  written from ads827x and ads85xx.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 8 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"

 

#define WRITEADR(reg1,reg2,addr32,val) \
	lis	reg1, HI(addr32); \
	ori	reg1, reg1, LO(addr32); \
	lis	reg2, HI(val); \
	ori	reg2, reg2, LO(val); \
	stw	reg2, 0(reg1)

#define WRITEOFFSET(regbase,reg2,offset,val) \
        lis	reg2, HI(val); \
        ori	reg2, reg2, LO(val); \
	stw	reg2, offset(regbase);
	
	/* internals */

	FUNC_EXPORT(_romInit)		/* start of system code */
	FUNC_EXPORT(romInit)		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	.text
/* 
Hard Reset Configuration Word (HRCW) See config.h/ads834x.h/target.ref for 
more info
*/
 .fill   8,1,HRCW_LOW_BYTE0 
 .fill   8,1,HRCW_LOW_BYTE1 
 .fill   8,1,HRCW_LOW_BYTE2 
 .fill   8,1,HRCW_LOW_BYTE3
 .fill   8,1,HRCW_HIGH_BYTE0 
 .fill   8,1,HRCW_HIGH_BYTE1 
 .fill   8,1,HRCW_HIGH_BYTE2 
 .fill   8,1,HRCW_HIGH_BYTE3

 .fill   192,1,0     /* The rest of the space are filled with zeros */

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:

        bl	cold		/* jump to the cold boot initialization */
	nop
	bl	warm		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Boot Image Wind River Systems, Inc."
	.align 2

cold:
        li      r3, BOOT_COLD   /* set cold boot as start type */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification. The default IMMR base address was 0xFF400000,
	 * as originally programmed in the Hard Reset Configuration Word.
	 */


	lis	r4, HI (CCSBAR)	
	ori	r4, r4, LO (CCSBAR)
	
	lis     r8,HIADJ(CCSBAR_INIT)	/* IMMR was at 0xff400000 */
	ori     r8, r8, LO(CCSBAR_INIT)	/* IMMR now at CCSBAR */
	stw     r4,0(r8)
	isync
	sync

	

        sync
        isync
			
	lis  r5, HIADJ(QUICC_OR0(CCSBAR))
	addi r5, r5, LO(QUICC_OR0(CCSBAR))

	lwz  r6, 0(r5)
	ori  r6, r6, 0xff7
	stw  r6, 0(r5) 
	isync			/* synchronize */
	
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,0), 0x00000000)

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,0), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_2GB ))

	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,0))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,0))
	lwz  r7,0(r6)
	
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,1), 0x80000000)

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,1), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_2GB ) )
	
	lis  r6,HI(M83XX_LBLAWARn(CCSBAR,1))
	ori  r6,r6,LO(M83XX_LBLAWARn(CCSBAR,1))
	lwz  r7,0(r6)
	
	isync
		
	/*
	 * When the PowerPC 83xx is powered on, the processor fetches the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */

        lis     r4, HIADJ(start)                /* load r4 with the address */
        addi    r4, r4, LO(start)               /* of start */
 
        lis     r5, HIADJ(romInit)              /* load r5 with the address */
        addi    r5, r5, LO(romInit)             /* of romInit() */
 
        lis     r6, HIADJ(ROM_TEXT_ADRS)        /* load r6 with the address */
        addi    r6, r6, LO(ROM_TEXT_ADRS)       /* of ROM_TEXT_ADRS */
 
        sub     r4, r4, r5                      /*  */
        add     r4, r4, r6
 
        mtspr   LR, r4                          /* save destination address*/
                                                /* into LR register */
        blr                                     /* jump to flash mem address */
start:

	/* set the MSR register to a known state */

	xor	r0, r0, r0		/* clear register R0 */
	isync				/* synchronize */
	mtmsr 	r0			/* clear the MSR register */
	sync
	isync				/* synchronize */

	WRITEADR(r6,r7,QUICC_BR0(CCSBAR),ROM_BASE_ADRS|0x1001)
	
	WRITEADR(r6,r7,QUICC_OR0(CCSBAR),0xFF006FF7) 

	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,0), ROM_BASE_ADRS)

	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,0), \
		 (LAWAR_ENABLE |  LAWAR_SIZE_16MB ))




	WRITEADR(r6,r7,M83XX_LBLAWARn(CCSBAR,1), 0x00000000)
	WRITEADR(r6,r7,M83XX_LBLAWBARn(CCSBAR,1), 0x10000000)
		
	WRITEADR(r6,r7, M83XX_SICRL(CCSBAR),0xC0000000)
	isync
	WRITEADR(r6,r7, M83XX_SICRH(CCSBAR),0x00000002)
	isync

	WRITEADR(r6,r7, M83XX_RMR(CCSBAR),0x00000001)
	isync
	WRITEADR(r6,r7, M83XX_RSR(CCSBAR),0xffffffff)
	isync
	
        /* disable clocks, peripheral driver or sysHwInit() will start  */
        WRITEADR(r6,r7, QUICC_LBCR(CCSBAR),0)
	isync
	
	
	/* Initialise the Local Bus Controller */
	WRITEADR(r6,r7,QUICC_LCRR(CCSBAR),0x80000004) 

	
	li  r6,0x0020
	mtctr r6
lbcdelay:
	nop
	bdnz lbcdelay
	nop
	isync
	sync
	
	mtspr   1008, r0        /* HID0 */
        isync
	
         /* Zero-out registers: SPRGs */
 
	addis    r0,0,0
	isync				/* synchronize */

        mtspr   272,r0
        mtspr   273,r0
        mtspr   274,r0
        mtspr   275,r0
	isync				/* synchronize */
 
        /* zero-out the Segment registers */
 
        mtsr    0,r0
        isync
        mtsr    1,r0
        isync
        mtsr    2,r0
        isync
        mtsr    3,r0
        isync
        mtsr    4,r0
        isync
        mtsr    5,r0
        isync
        mtsr    6,r0
        isync
        mtsr    7,r0
        isync
        mtsr    8,r0
        isync
        mtsr    9,r0
        isync
        mtsr    10,r0
        isync
        mtsr    11,r0
        isync
        mtsr    12,r0
        isync
        mtsr    13,r0
        isync
        mtsr    14,r0
        isync
        mtsr    15,r0
        isync
 
	/* invalidate DBATs: clear VP and VS bits */

	mtspr   536,r0   /* Data bat register 0 upper */
	isync
	mtspr   538,r0   /* Data bat register 1 upper */
	isync
	mtspr   540,r0   /* Data bat register 2 upper */
	isync
	mtspr   542,r0   /* Data bat register 3 upper */
	isync
	
	/* invalidate IBATs: clear VP and VS bits */

	mtspr   528,r0   /* Instruction bat register 0 upper */
	isync
	mtspr   530,r0   /* Instruction bat register 1 upper */
	isync
	mtspr   532,r0   /* Instruction bat register 2 upper */
	isync
	mtspr   534,r0   /* Instruction bat register 3 upper */
	isync

	/* invalidate TLBs: loop on all TLB entries using r7 as an index */

	addi     r0,0,0x0020
	mtspr    9,r0			/* Load CTR with 32 */
	addi     r7,0,0            	/* Use r7 as the tlb index */
 
tlb_write_loop:
 
	tlbie    r7                	/* invalidate the tlb entry */
	sync
	addi     r7,r7,0x1000          	/* increment the index */
	bc       16,0,tlb_write_loop   	/* Decrement CTR, then branch if the */
				       	/* decremented CTR is not equal to 0 */

        /* Turn off data and instruction cache control bits */
 
        mfspr   r7, HID0
        isync
	sync				/* synchronize */