mot83xxpci.c

MPC8360MDS VXWORKS BSP

/* mot83xxPci.c - Motorola ads 83xx PCI Bridge functions */

/*
 * Copyright (c) 2003-2005 Wind River Systems, Inc.
 *
 * The right to copy, distribute or otherwise make use of this software
 * may be licensed only pursuant to the terms of an applicable Wind River
 * license agreement. No license to Wind River intellectual property rights
 * is granted herein. All rights not licensed by Wind River are reserved
 * by Wind River.
 */

#include "copyright_wrs.h"

/*
modification history
--------------------
01d,11oct05,dtr  Fix SPR 113600.
01c,03aug05,dtr  Add support for PCI2.
01b,04apr05,mdo  Documentation fixes for apigen
01a,04feb05,dtr  File created from mot85xxPci.c.
*/

/*
DESCRIPTION
This file contains the PCI Host Bridge setup File.

INCLUDE FILES:
*/

#include "vxWorks.h"
#include "config.h"
#include "sysLib.h"

#include "drv/pci/pciConfigLib.h" 	
#include "drv/pci/pciIntLib.h" 	
#include "drv/pci/pciAutoConfigLib.h"	
#include "sysBusPci.h"
#include "mot83xxPci.h"

#define MAX_NUM_VECTORS 4

UINT32 pciRegRead(UINT32 *adrs);
void   pciRegWrite(UINT32 *adrs,UINT32 value);

void pciConfigTest(int);
#define PCI_REG_READ  pciRegRead
#define PCI_REG_WRITE  pciRegWrite


/*************************************************************************
* 
* mot83xxBridgeInit - initialize the PCI Bridge
*
* This function performs all the initialization required for the 
* Bridge/Interrupts/PCI Bus to function. It does some low level processor 
* initialization which might normally be done in romInit as it is optional 
* to do use this and shows what the core changes required to bring up the 
* bridge.
* 
* RETURNS: N/A
*
* ERRNO
*/


void mot83xxBridgeInit (void)
    {
    STATUS result;

    *PCI1_GCR(CCSBAR) = 0x1; /* Clear PCI reset */

    /* Allow time for PCI Bus to come out of reset */ 
    {
        volatile int i;
        for (i = 0 ; i < 0x80000 ; i++) 
	    WRS_ASM("isync");

    }

    *PCI1_GCR(CCSBAR) = 0x0; /*  PCI reset */

    /* Allow time for PCI Bus to reset */ 
    {
        volatile int i;
        for (i = 0 ; i < 0x80000 ; i++) 
	    WRS_ASM("isync");

    }
    *PCI1_GCR(CCSBAR) = 0x1; /* Clear PCI reset */

    /* Allow time for PCI Bus to come out of reset */ 
    {
        volatile int i;
        for (i = 0 ; i < 0x80000 ; i++) 
	    WRS_ASM("isync");

    }


    /* Initialize LAWBAR/LAWAR for PCI */


    *M83XX_PCILAWBARn(CCSBAR,0) = CPU_PCI_MEM_ADRS ;
    *M83XX_PCILAWARn(CCSBAR,0) = LAWAR_ENABLE  | LAWAR_SIZE_256MB;

    *PCI1_ECR(CCSBAR) = 0x0; /* Generate interrupt if PCI error and ESR set*/
    *PCI1_ESR(CCSBAR) = 0xffffffff; /* Clear status */


#ifdef INCLUDE_SECONDARY_PCI 

    /* Allow time for PCI Bus to come out of reset */ 
    {
        volatile int i;
        for (i = 0 ; i < 0x100000 ; i++) 
	    WRS_ASM("isync");

    }
    *PCI2_GCR(CCSBAR) = 0x1; /* Clear PCI reset */

    /* Allow time for PCI Bus to come out of reset */ 
    {
        volatile int i;
        for (i = 0 ; i < 0x100000 ; i++) 
	    WRS_ASM("isync");

    }

    *M83XX_PCILAWBARn(CCSBAR,1) = CPU_PCI2_MEM_ADRS ;
    *M83XX_PCILAWARn(CCSBAR,1) = LAWAR_ENABLE  | LAWAR_SIZE_256MB;

    *PCI2_ECR(CCSBAR) = 0x0; /* Generate interrupt if PCI error and ESR set*/
    *PCI2_ESR(CCSBAR) = 0xffffffff; /* Clear status */


#endif/* INCLUDE_SECONDARY_PCI */
    /* May need to handle target abort */


    sysPciConfigEnable(PCI_1_BUS);

    /* Set outbound translation window addresses */

    result = sysPciConfigWrite(0,0,0,
                               PCI_CFG_BASE_ADDRESS_0,
                               0x4,
                               PCI_BRIDGE_PIMMR_BASE_ADRS);


    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,0)),
                  CPU_PCI_MEM_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REGn(CCSBAR,0)),
                  PCI_MEM_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,1)),
                  CPU_PCI_MEMIO_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REGn(CCSBAR,1)),
                  PCI_MEMIO_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,2)),
                  CPU_PCI_IO_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,2)),
                  PCI_IO_ADRS >> 12);


    /* Switch on the outbound translation windows */
    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,0)),
                  0xa00f8000); /* Enable|128MB */

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,1)),
                  0xa00fc000); /* Enable|64MB */

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,2)),
                  0xc00fc000); /* Enable|64MB */

    PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_BASE_ADRS_REGn(CCSBAR,1)),
                  0);

    PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_TRANS_ADRS_REGn(CCSBAR,1)),
                  0);

    PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,1)),
                  PCI_WINDOW_ENABLE_BIT | 
                  PCI_IN_ATTR_RTT_LM_WRITE_SNOOP | 
                  PCI_IN_ATTR_RTT_LM_READ_SNOOP | 
                  PCI_ATTR_WS_256M);

    PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,2)),
                  0x0);
    PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,3)),
                  0x0);


    /* configure the bridge as bus master */

    result = sysPciConfigWrite(0,0,0,
                               COMMAND_REGISTER_OFFSET,
                               COMMAND_REGISTER_WIDTH,
                               PCI_CMD_IO_ENABLE |
                               PCI_CMD_MEM_ENABLE | 
                               PCI_CMD_MASTER_ENABLE);


#ifdef INCLUDE_SECONDARY_PCI

    sysPciConfigEnable(PCI_2_BUS);

    /* Set outbound translation window addresses */

    result = sysPciConfigWrite(0,0,0,
                               PCI_CFG_BASE_ADDRESS_0,
                               0x4,
                               PCI_BRIDGE_PIMMR_BASE_ADRS);


    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,2)),
                  CPU_PCI_MEM_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REGn(CCSBAR,2)),
                  PCI_MEM_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,3)),
                  CPU_PCI_MEMIO_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REGn(CCSBAR,3)),
                  PCI_MEMIO_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,4)),
                  CPU_PCI_IO_ADRS >> 12);

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,4)),
                  PCI_IO_ADRS >> 12);

    /* Switch on the outbound translation windows */
    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,2)),
                  0xb00f8000); /* Enable|Prefetchable|256MB|PCI2 */

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,3)),
                  0xb00fc000); /* Enable|Prefetchable|256MB|PCI2 */

    PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,4)),
                  0xd00fc000); /* Enable|Prefetchable|256MB|PCI2|IO */

    PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_BASE_ADRS_REGn(CCSBAR,1)),
                  0);

    PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_TRANS_ADRS_REGn(CCSBAR,1)),
                  0);

    PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_ATTR_REGn(CCSBAR,1)),
                  PCI_WINDOW_ENABLE_BIT | 
                  PCI_IN_ATTR_RTT_LM_WRITE_SNOOP | 
                  PCI_IN_ATTR_RTT_LM_READ_SNOOP | 
                  PCI_ATTR_WS_256M);

    PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_ATTR_REGn(CCSBAR,2)),
                  0x0);
    PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_ATTR_REGn(CCSBAR,3)),
                  0x0);


    /* configure the bridge as bus master */

    result = sysPciConfigWrite(0,0,0,
                               COMMAND_REGISTER_OFFSET,
                               COMMAND_REGISTER_WIDTH,
                               PCI_CMD_IO_ENABLE |
                               PCI_CMD_MEM_ENABLE | 
                               PCI_CMD_MASTER_ENABLE);
#endif

    sysPciConfigEnable(PCI_1_BUS);

    }


void pciRegWrite
    (
    UINT32 *adrs,
    UINT32 value
    )
    {
    *adrs = value;
    WRS_ASM("isync;sync");
    }

UINT32 pciRegRead
    (
    UINT32 *adrs
    )
    {
    return(*adrs);
    }


/***********************************************************
* pciConfigTest - dump on-chip PCI configuration header
*
* This function print out PCI configuration header.
* 
* RETURNS: N/A
*
* ERRNO
*/

void pciConfigTest
    (
    int pciSys
    )
    {
    int loop;
    UINT32 var;

    if (pciSys == PCI_2_BUS)
        sysPciConfigEnable (PCI_2_BUS);
    else
        sysPciConfigEnable (PCI_1_BUS);

    for(loop = 0; loop < 0x40; loop += 4)
        {
        sysPciConfigRead(0,0,0,loop,0x4,&var);
        printf("Word %d Value %x\n",loop,var);
        }
    }