mds8360.h

MPC8360MDS VXWORKS BSP

/* ads834x.h - Motorola MPC834x ADS board header */

/* Copyright 1984-2005 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,07jun06,dtr  Add CMXUPCR reg definitions.
01a,16mar05,dtr  adapted from ads834x.h
*/

/*
This file contains I/O addresses and related constants for the
Motorola MPC8360 MDS board.
*/

#ifndef	INCads834xh
#define	INCads834xh

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

#ifndef  _ASMLANGUAGE
# if (defined(_WRS_VXWORKS_MAJOR) && (_WRS_VXWORKS_MAJOR >= 6))
/* nothing needed */
# else  /* _WRS_VXWORKS_MAJOR */
typedef void * VIRT_ADDR;
typedef void * PHYS_ADDR;
# endif  /* _WRS_VXWORKS_MAJOR */
#endif  /* _ASMLANGUAGE */

#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS

#ifdef  _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR;   /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8;   /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;   /* volatile unsigned byte */
#define CAST(x) (x)
#endif  /* _ASMLANGUAGE */

#endif /* M8260ABBREVIATIONS */

#define N_SIO_CHANNELS	 	2		/* No. serial I/O channels */

/* define the decrementer input clock frequency */
#define SPD_DATA_SIZE         128
#undef  BOOT_LINE_SIZE
#define BOOT_LINE_SIZE        256
#define NV_RAM_SIZE_WRITEABLE NV_RAM_SIZE  /* force VTS to only use 128 bytes */
#define MAX_MAC_ADRS 2
#define MAC_ADRS_LEN 6

#define WR_ENET0  	    0x00  /* WR specific portion of MAC (MSB->LSB) */
#define WR_ENET1  	    0xA0
#define WR_ENET2  	    0x1E

#define CUST_ENET3_0    0xA0  /* Customer portion of MAC address */
#define CUST_ENET3_1    0xA1
#define CUST_ENET4 	0xAA
#define CUST_ENET5      0xA0


/* Base Address of Memory Mapped Registers */
#define CCSBAR_INIT  0xFF400000
#define CCSBAR       0xE0000000
#define CCSBAR_SIZE  0x400000 /* 1MB */

/* Defines used for driver features*/
#define PQ2PRO_QE
#define QUICC_ENGINE
#define USE_MUX_LAYER

/* Register Set Base addresses */
#define SCCFG_REG_BA           0x00100 
#define WDT_REG_BA             0x00200
#define QUICC_RTC_BASE         0x00300
#define QUICC_PIT_BASE         0x00400
#define QUICC_GTM1_BASE        0x00500
#define QUICC_GTM2_BASE        0x00600
#define SIC_REG_BA             0x00700
#define ARBITER_REG_BA         0x00800
#define RESETM_REG_BA          0x00900

#define CLKM_REG_BA            0x00A00

#define QE_PORT_INTERRUPTS     0x00C00

#define QE_IO_PORTS            0x01400
#define QE_SEC_BA_WINDOWS      0x01800

#define DDR_REG_BA             0x02000
#define LBC_REG_BA             0x05000
#define DMA_REG_BA             0x08100
#define PCICFG_REG_BA          0x08300
#define PCI2CFG_REG_BA         0x08380
#define SEC_REG_BA             0x101B4
#define QUICC_ENGINE_BA        0x100000
#define QE_MURAM_BA            0x010000
#define DMA_NUM 4

#define UCC1_BASE 0x2000
#define UCC2_BASE 0x3000
#define UCC3_BASE 0x2200
#define UCC4_BASE 0x3200
#define UCC5_BASE 0x2400
#define UCC6_BASE 0x3400
#define UCC7_BASE 0x2600
#define UCC8_BASE 0x3600

#define QE_MUX (QUICC_ENGINE_BA + 0x400)

/* CPM mux FCC clock route register */

#define QE_CMXUCR1(base)   (CAST(VUINT32 *)((base) + QE_MUX + 0x10))
#define QE_CMXUCR2(base)   (CAST(VUINT32 *)((base) + QE_MUX + 0x14))
#define QE_CMXUCR3(base)   (CAST(VUINT32 *)((base) + QE_MUX + 0x18))
#define QE_CMXUCR4(base)   (CAST(VUINT32 *)((base) + QE_MUX + 0x1C))
#define QE_CMXUPCR(base)   (CAST(VUINT32 *)((base) + QE_MUX + 0x22))


#define QE_SDMA (QUICC_ENGINE_BA + 0x4000)

/* CPM mux FCC clock route register */

#define QE_SDSR(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x00))
#define QE_SDMR(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x04))
#define QE_SDTR1(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x08))
#define QE_SDTR2(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x0C))
#define QE_SDHY1(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x10))
#define QE_SDHY2(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x14))
#define QE_SDTA1(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x18)) /* read only
 */
#define QE_SDTA2(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x1C))/* read only 
*/
#define QE_SDTM1(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x20))/* read only 
*/
#define QE_SDTM2(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x24))/* read only 
*/

#define QE_SDAQR(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x38))
#define QE_SDAQMR(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x3C))

#define QE_SDEBCR(base)   (CAST(VUINT32 *)((base) + QE_SDMA + 0x44))

/* Define the register definition and interrupt numbers based on 
 * cpu varient */

#include <drv/intrCtl/quiccIntrCtl.h>
#include <drv/mem/quiccLbc.h>

/* system & processor version */


/* System Configuration Control */

#define M83XX_SGPRL(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x00 ))
#define M83XX_SGPRH(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x04 ))
#define M83XX_SPRIDR(base) (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x08 ))


#define M83XX_SPCR(base)  (CAST(VUINT32 *)((base) +  SCCFG_REG_BA + 0x10 ))
#define M83XX_SPCR_OPT 0x00800000
#define M83XX_SPCR_TBEN 0x00400000

#define M83XX_SICRL(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x14 ))
#define M83XX_SICRH(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x18 ))



/* Watch Dog Registers */

#define M83XX_SWCRR(base)  (CAST(VUINT32 *)((base) + WDT_REG_BA + 0x04 ))
#define M83XX_SWCNR(base)  (CAST(VUINT32 *)((base) + WDT_REG_BA + 0x08 ))
#define M83XX_SWSRR(base)  (CAST(VUINT16 *)((base) + WDT_REG_BA + 0x0E ))


/* Clock Module */
#define M83XX_SPMR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x00 ))
#define M83XX_SPMR_LBIU_VAL(spmrVal) (spmrVal >> 31);
#define M83XX_SPMR_DDR_VAL(spmrVal) (spmrVal >> 30) & 0x1;
#define M83XX_SPMR_SPMF_VAL(spmrVal) (spmrVal >> 24) & 0xf;
#define M83XX_SPMR_CLK_DIV(spmrVal) (spmrVal >> 23) & 0x1;
#define M83XX_SPMR_CLK_PLL(spmrVal) (spmrVal >> 16) & 0x7f;

#define M83XX_OCCR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x04 ))
#define M83XX_SCCR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x08 ))

#define M83XX_SCCR_RES_MSK      0xf3f10000      /* reserved field Mask */

/* Arbiter registers*/

#define M83XX_ACR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x00))
#define M83XX_ATR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x04))
#define M83XX_AER(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x0c))
#define M83XX_AIDR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x10))
#define M83XX_AMR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x14))
#define M83XX_AEATR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x18))
#define M83XX_AEADR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x1c))
#define M83XX_AERR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x20))

/* Reset Configuration Module */

#define M83XX_RCWLR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x00))
#define M83XX_RCWHR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x04))
#define M83XX_RSR(base)     (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x10))
#define M83XX_RMR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x14))
#define M83XX_RPR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x18))
#define M83XX_RCR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x1c))
#define M83XX_RCER(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x20))


/* I2C1 Controller */

#define  M834X_I2C1_BASE                 0x03000 

#define  I2C1ADR    0x03000
#define  I2C1FDR    0x03004
#define  I2C1ICR    0x03008
#define  I2C1ISR    0x0300c
#define  I2C1IDR    0x03010
#define  I2C1DFSRR  0x03014

#define  M834X_I2C1ADR(base)            (CAST(VUINT8 *)((base) | I2C1ADR))
#define  M834X_I2C1FDR(base)            (CAST(VUINT8 *)((base) | I2C1FDR))
#define  M834X_I2C1ICR(base)            (CAST(VUINT8 *)((base) | I2C1ICR))
#define  M834X_I2C1ISR(base)            (CAST(VUINT8 *)((base) | I2C1ISR))
#define  M834X_I2C1IDR(base)            (CAST(VUINT8 *)((base) | I2C1IDR))
#define  M834X_I2C1DFSRR(base)          (CAST(VUINT32 *)((base) | I2C1DFSRR))


/* I2C2 Controller */

#define  M834X_I2C2_BASE                 0x03100 

#define  I2C2ADR    0x03100
#define  I2C2FDR    0x03104
#define  I2C2ICR    0x03108
#define  I2C2ISR    0x0310c
#define  I2C2IDR    0x03110
#define  I2C2DFSRR  0x03114

#define  M834X_I2C2ADR(base)            (CAST(VUINT8 *)((base) | I2C2ADR))
#define  M834X_I2C2FDR(base)            (CAST(VUINT8 *)((base) | I2C2FDR))
#define  M834X_I2C2ICR(base)            (CAST(VUINT8 *)((base) | I2C2ICR))
#define  M834X_I2C2ISR(base)            (CAST(VUINT8 *)((base) | I2C2ISR))
#define  M834X_I2C2IDR(base)            (CAST(VUINT8 *)((base) | I2C2IDR))
#define  M834X_I2C2DFSRR(base)          (CAST(VUINT32 *)((base) | I2C2DFSRR))


/* Security IMMR registers */
#define QUICC_SECBR(base) (CAST(VUINT32 *)((base) + SEC_REG_BA + 0x0)) 
#define QUICC_SECMR(base) (CAST(VUINT32 *)((base) + SEC_REG_BA + 0x4))

#define SEC_ENG_BASE_ADRS (CCSBAR + 0x40000)
#define SEC_ENG_SIZE      0x20000
#define SEC_ENG_SIZE_MASK 0xfffe0000

/* USB MPH (Host) registers */

/* These are little-endian */
#define  M83XX_CAPLENGTH(base)           (CAST(VUINT8  *)((base) | 0x22100))
#define  M83XX_HCIVERSION(base)          (CAST(VUINT16 *)((base) | 0x22102))
#define  M83XX_HCSPARAMS_L(base)         (CAST(VUINT32 *)((base) | 0x22104))
#define  M83XX_HCSPARAMS_H(base)         (CAST(VUINT32 *)((base) | 0x22108))

#define  M83XX_USBCMD(base)              (CAST(VUINT32 *)((base) | 0x22140))
#define  M83XX_USBSTS(base)              (CAST(VUINT32 *)((base) | 0x22144))
#define  M83XX_USBINTR(base)             (CAST(VUINT32 *)((base) | 0x22148))
#define  M83XX_FRINDEX(base)             (CAST(VUINT32 *)((base) | 0x2214c))
#define  M83XX_PERIODICLISTBASE(base)    (CAST(VUINT32 *)((base) | 0x22154))
#define  M83XX_ASYNCLISTADDR(base)       (CAST(VUINT32 *)((base) | 0x22158))
#define  M83XX_ASYNCTTSTS(base)          (CAST(VUINT32 *)((base) | 0x2215c))
#define  M83XX_BURSTSIZE(base)           (CAST(VUINT32 *)((base) | 0x22160))
#define  M83XX_TXTTFILLTUNING_L(base)    (CAST(VUINT32 *)((base) | 0x22164))
#define  M83XX_TXTTFILLTUNING_H(base)    (CAST(VUINT32 *)((base) | 0x22168))
#define  M83XX_CONFIGFLAG(base)          (CAST(VUINT32 *)((base) | 0x22180))
#define  M83XX_PORTSC1(base)             (CAST(VUINT32 *)((base) | 0x22184))
#define  M83XX_PORTSC2(base)             (CAST(VUINT32 *)((base) | 0x22188))
#define  M83XX_USBMODE(base)             (CAST(VUINT32 *)((base) | 0x221a8))

/* These are big-endian */
#define  M83XX_SNOOP1(base)              (CAST(VUINT32 *)((base) | 0x22400))
#define  M83XX_SNOOP2(base)              (CAST(VUINT32 *)((base) | 0x22404))
#define  M83XX_AGE_CNT_THRESH(base)      (CAST(VUINT32 *)((base) | 0x22408))
#define  M83XX_PRI_CTRL(base)            (CAST(VUINT32 *)((base) | 0x2240c))
#define  M83XX_SI_CTRL(base)             (CAST(VUINT32 *)((base) | 0x22410))
#define  M83XX_CONTROL(base)             (CAST(VUINT32 *)((base) | 0x22500))


/* Local address windows */

#define M83XX_LBLAWBARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x20 + (n*0x8)))

#define M83XX_LBLAWARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x24 + (n*0x8)))

#define M83XX_PCILAWBARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x60 + (n*0x8)))

#define M83XX_PCILAWARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x64 + (n*0x8)))

#define M83XX_DDRLAWBARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0xA0 + (n*0x8)))

#define M83XX_DDRLAWARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0xA4 + (n*0x8)))

#define LAWBAR_ADRS_SHIFT  0

#define  LAWAR_ENABLE       0x80000000
/* LAWAR SIZE Settings */ 
#define  LAWAR_SIZE_4KB     0x0000000B
#define  LAWAR_SIZE_8KB     0x0000000C
#define  LAWAR_SIZE_16KB    0x0000000D
#define  LAWAR_SIZE_32KB    0x0000000E
#define  LAWAR_SIZE_64KB    0x0000000F
#define  LAWAR_SIZE_128KB   0x00000010
#define  LAWAR_SIZE_256KB   0x00000011
#define  LAWAR_SIZE_512KB   0x00000012
#define  LAWAR_SIZE_1MB     0x00000013
#define  LAWAR_SIZE_2MB     0x00000014
#define  LAWAR_SIZE_4MB     0x00000015
#define  LAWAR_SIZE_8MB     0x00000016
#define  LAWAR_SIZE_16MB    0x00000017
#define  LAWAR_SIZE_32MB    0x00000018
#define  LAWAR_SIZE_64MB    0x00000019