hwconf.c

MPC8360MDS VXWORKS BSP

/* hwconf.c - Hardware configuration support module */

/* Copyright (c) 2005-2006 Wind River Systems, Inc. */

/*
modification history
--------------------
01g,07feb06,wap  Add VxBus parameter table
01f,04jan06,wap  Correct TSEC setup so interrupts work
01e,26oct05,mdo  renaming header files
01d,15sep05,to   
01c,14sep05,mdo  Add vxb prefix
01b,08aug05,mdo  Change WINDBUS to VXBUS
01a,28jul05,rls  Created.
*/

#include <vxWorks.h>
#include <vxBusLib.h>
#include <hwif/vxbus/vxBus.h>
#include <hwif/vxbus/hwConf.h>
#include <hwif/util/vxbParamSys.h>
#include <drv/intrCtl/qeIntrCtl.h>
#include "config.h"
#include "sysDuart.h"

/* vxBus resource files for onboard UARTS */

const struct hcfResource ns1655x1Resources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *)COM1_ADR} },
        { "irq",         HCF_RES_INT, {(void *)INUM_UART1} },
        { "regInterval", HCF_RES_INT, {(void *)DUART_REG_ADDR_INTERVAL} },
        { "irqLevel",    HCF_RES_INT, {(void *)INUM_UART1} },
        { "clkFreq",	 HCF_RES_ADDR, {(void *)&sysClkFreqGet} }

    };

#define ns1655x1Num NELEMENTS(ns1655x1Resources)

const struct hcfResource ns1655x2Resources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *)COM2_ADR} },
        { "irq",         HCF_RES_INT, {(void *)INUM_UART2} },
        { "regInterval", HCF_RES_INT, {(void *)DUART_REG_ADDR_INTERVAL} },
        { "irqLevel",    HCF_RES_INT, {(void *)INUM_UART2} },
        { "clkFreq",	 HCF_RES_ADDR, {(void *)&sysClkFreqGet} }

    };
#define ns1655x2Num NELEMENTS(ns1655x2Resources)

const struct hcfResource qefccHEnd0Resources[] = {
    { "regBase", HCF_RES_INT, { (void *)(CCSBAR + QUICC_ENGINE_BA + UCC1_BASE) } },
    { "txInt", HCF_RES_INT, { (void *)(QE_INUM_UCC1 + IVEC_MAX) } },
    { "txIntLevel", HCF_RES_INT, { (void *)(QE_INUM_UCC1 + IVEC_MAX) } }
};
#define qefccHEnd0Num NELEMENTS(qefccHEnd0Resources)

const struct hcfResource qefccHEnd1Resources[] = {
    { "regBase", HCF_RES_INT, { (void *)(CCSBAR + QUICC_ENGINE_BA + UCC2_BASE) } },
    { "txInt", HCF_RES_INT, { (void *)(QE_INUM_UCC2 + IVEC_MAX) } },
    { "txIntLevel", HCF_RES_INT, { (void *)(QE_INUM_UCC2 + IVEC_MAX) } }
};
#define qefccHEnd1Num NELEMENTS(qefccHEnd1Resources)

const struct hcfResource phy0Resources[] = {
    { "realBus", HCF_RES_INT, { (void *)0 } },
    { "phyAddr", HCF_RES_INT, { (void *)1 } },
    { "virtBus", HCF_RES_INT, { (void *)1 } }
    };

#define phy0Num NELEMENTS(phy0Resources)

const struct hcfResource quiccEngineResources[] = 
    {
    { "regBase", HCF_RES_INT, { (void *)(CCSBAR + QUICC_ENGINE_BA) } },
    { "muRamBase1", HCF_RES_INT, { (void *)(CCSBAR + QUICC_ENGINE_BA + QE_MURAM_BA) }},
    { "muRamBase2", HCF_RES_INT, { (void *)(CCSBAR + QUICC_ENGINE_BA + QE_MURAM_BA + 0x100) }},
    { "qeVersion", HCF_RES_INT, { (void *)(0) }},
    { "muRamPool1Size", HCF_RES_INT, { (void *)(0x100) }},
    { "muRamPool2Size", HCF_RES_INT, { (void *)(0xc000 - 0x100) }}
    };




#define quiccEngine0Num NELEMENTS(quiccEngineResources)

const struct hcfDevice hcfDeviceList[] = 
    {
    { "qefccHEnd",0,VXB_BUSID_PLB, 0, qefccHEnd0Num, qefccHEnd0Resources },
    { "qefccHEnd",1,VXB_BUSID_PLB, 0, qefccHEnd1Num, qefccHEnd1Resources },
    { "phy", 1, VXB_BUSID_MII, 0, phy0Num, phy0Resources },
    { "ns16550", 0, VXB_BUSID_PLB, 0, ns1655x1Num, ns1655x1Resources },
    { "ns16550", 1, VXB_BUSID_PLB, 0, ns1655x2Num, ns1655x2Resources },
    { "quiccEngine",0,VXB_BUSID_PLB, 0,quiccEngine0Num,quiccEngineResources}
    };

const int hcfDeviceNum = NELEMENTS(hcfDeviceList);

    
VXB_INST_PARAM_OVERRIDE sysInstParamTable[] =
    {
    { NULL, 0, NULL, VXB_PARAM_END_OF_LIST, {(void *)0} }
    };