singt.map.qmsg

dds正弦可控发生计全结果 用到matlab

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 23 12:24:23 2008 " "Info: Processing started: Tue Dec 23 12:24:23 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off singt -c singt " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off singt -c singt" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/altera/DSPBuilder/Altlib/DSPBUILDERPACK.VHD " "Warning: Can't analyze file -- file C:/altera/DSPBuilder/Altlib/DSPBUILDERPACK.VHD is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD " "Warning: Can't analyze file -- file C:/altera/DSPBuilder/Altlib/DSPBUILDER.VHD is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "singt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file singt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 singt-aDspBuilder " "Info: Found design unit 1: singt-aDspBuilder" {  } { { "singt.vhd" "" { Text "E:/Ljltx/Sinout/singt.vhd" 41 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 singt " "Info: Found entity 1: singt" {  } { { "singt.vhd" "" { Text "E:/Ljltx/Sinout/singt.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_IS_NOT_COMPILED_IN_LIBRARY" "dspbuilderblock dspbuilder singt.vhd(27) " "Error (10481): VHDL Use Clause error at singt.vhd(27): design library \"dspbuilder\" does not contain primary unit \"dspbuilderblock\"" {  } { { "singt.vhd" "" { Text "E:/Ljltx/Sinout/singt.vhd" 27 0 0 } }  } 0 10481 "VHDL Use Clause error at %3!s!: design library \"%2!s!\" does not contain primary unit \"%1!s!\"" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  2 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 2 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Dec 23 12:24:24 2008 " "Error: Processing ended: Tue Dec 23 12:24:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}