📄 singt_dspbuilder_report.html
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<title>SignalCompiler report e:\ljltx\sinout\singt_DspBuilder_Report.html</title>
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<h3> SignalCompiler report </h3>
<i><h5>Use the right-click mouse button to naviguate through singt_DspBuilder_Report.html
</h5></i><hr><h3>Project Setting</h3><TABLE>
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<TD><b>Model</b> </TD> <TD> singt</TD>
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<TD><b>Directory</b> </TD> <TD> e:\ljltx\sinout</TD>
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<TD><b>Device family</b> </TD> <TD>Cyclone</TD>
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<TD><b>Synthesis tool</b> </TD> <TD>Quartus II</TD>
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<TD> <b>Optimization </b></TD> <TD>Balanced</TD>
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<TD> <b>Date</b> </TD> <TD>Thursday, December 18, 2008</TD>
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<TD> <b>Time</b> </TD> <TD>01:31:06</TD>
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<TD><b>Version</b> </TD> <TD> 6.0 Internal Build 180</TD>
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<h3>Compilation status</h3>
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<TD>Convert Mdl to VHDL </TD> <TD><b>:</b> PASSED </TD><TD></TD>
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<TD>Synthesis </TD> <TD><b>:</b><font color="red"> FAILED </font></TD><TD><A HREF="singt.map.rpt">singt.map.rpt</A></TD>
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<TR><TD>Quartus II Fitter</TD> <TD><b>:</b><font color="red"> FAILED </font></TD><TD><A HREF="singt.fit.rpt">singt.fit.rpt</A></TD></TR>
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<!--<h3>Resource Usage Summary</h3>-->
<!--<h3>Resource Utilization</h3>-->
<!--<h3>Timing Analyzer Summary</h3>-->
<h3>Pin-Out</h3><TABLE>
<TR><TD><b>Pin name </b></TD>
<TD><b>Pin Direction </b></TD>
<TD><b>Bus Type </b></TD></TR>
<TR><TD> clock </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> sclrp </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> SinCtrl </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> SinOut </TD><TD> out </TD><TD>std_logic_vector(7 downto 0) )</TD></TR><TR><TD></TR></TABLE><br>
<p><b>Clock input pin (clock):</b>
All registered blocks use the input clock signal <b>'clock'</b>. singt.mdl does not use PLL.<br><b>Reset input pin (sclrp):</b>
All registered blocks use the global reset input signal <b>'sclrp'</b> , which is synchronous and active high</p><hr>
<h3>Files generated by SignalCompiler</h3><TABLE BORDER>
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<TD> <b>singt.vhd</b> </TD><TD>VHDL representation of the design for synthesis and simulation </TD>
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<TD> <b>singt_quartus.tcl</b> </TD><TD>Tcl script for Quartus<font size="-1"><sup>®</font></sup> II compilation. <p><I>When compiling the design manually in the Quartus II software, type </i><b>source singt_quartus.tcl </b><i> in the Quartus II tcl console (Auxiliary Windows). The Quartus II software executes the Tcl script that sets up the project and environment for your design.</I></p></TD>
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<TD> <b>singt.vec</b> </TD><TD>Quartus<font size="-1"><sup>®</font></sup> II simulation vector file </TD>
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<TD> <b>singt.bsf</b> </TD><TD>Quartus<font size="-1"><sup>®</font></sup> II symbol file</TD>
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<TD><b> tb_singt.vhd</b> </TD><TD>VHDL design testbench for simulation </TD>
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<TD> <b>tb_singt.tcl</b> </TD><TD>Tcl script for ModelSim simulation <p><I>type </i><b>do tb_singt.tcl </b><i> at Modelsim prompt.</p></TD>
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<TD><b> tb_singt.v</b> </TD><TD>Verilog design testbench for simulation with Quartus II Verilog Output File (.vo)</TD>
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<hr>
<h3>Synthesis & compilation log files</h3>
<!--<p><A HREF="singt.srr">Synplicity Log</A></p>-->
<!--<p><A HREF="exemplar.log">Leonardo Log</A></p>-->
<p><A HREF="singt.map.rpt" >Quartus II Map Log</A></p>
<p><A HREF="singt.fit.rpt">Quartus II Fit Log</A></p>
<hr>
<h3>Entity singt</h3>
<p><A HREF="DSPBuilder_singt\singtblockInfos.html">Information page</A> on the DSP Builder blocks used in singt.</p>
<h4>Warning Section</h4><p>
<b> Signals Out of Range </b>: This section lists the signals with a bit width greater than 51 bits. Fixed-point DSP Builder models support up to 51 bits of resolution. When the bit width grows over 51 bits, additional VHDL RTL simulations are recommended to estimate the effect of overflow and rounding introduced by double signals.</p><pre>
</pre>
<hr>
<TABLE><TR><TD align="left"><A HREF="http://www.altera.com/">www.altera.com</A></TD>
<TD> </TD><TD align="right"> <A HREF="D:\altera\DSPBuilder\AltLib\..\doc\ug_dspbuilderTOC.html">help</A></TD>
</TR></TABLE><hr>
DSP Builder <br>Quartus II development tool and MATLAB/Simulink Interface
<br>Version 6.0 Internal Build 180<p> Legal Notice: ⌨️ 快捷键说明
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