📄 singt1.err
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GenerateSampleERTMain off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "singt1"
Location [445, 219, 1025, 512]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [250, 115, 295, 165]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Reference
Name "Incount"
Ports [0, 1]
Position [15, 118, 70, 162]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Increment\nDecrement"
SourceType "HDLEntity AlteraBlockSet"
BusType "Unsigned Integer"
bwl "10"
bwr "0"
direction "Increment"
cst_display "0"
cst "0"
clken off
MaskValue "1"
ntsamp "-1"
SIGNALCOMPILER_PARAMS "HDLInputPortsMappingAltera;NOINPUT;HDLOutputPor"
"tsMappingAltera;result.10.0.u;HDLParameterMappingAltera;lpm_width.10.natural,"
"cst_val.\"0000000000\".string,lpm.0.natural,isunsigned.1.natural,SequenceLeng"
"th.1.natural,SequenceValue.1.natural,direction.0.natural;HDLImplicitPortsMapp"
"ingAltera;clock.clock, sclr.sclr,ena.VCC;HDLComponentNameAltera;IncDec;BusTyp"
"e;Unsigned Integer;bwl;10;bwr;0;clken;off;cst;0;direction;Increment;"
}
Block {
BlockType Reference
Name "Product"
Ports [2, 1]
Position [330, 128, 395, 177]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Product"
SourceType "Product AlteraBlockSet"
pipeline "0"
lpm off
eab off
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"0;"
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [545, 146, 575, 179]
Location [175, 282, 499, 521]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [254, 13, 323, 60]
ForegroundColor "blue"
SourceBlock "Altelink/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Cyclone"
opt "Balanced"
synthtool "Others"
vstim on
SynthAct "None"
workdir "e:\\ljltx\\sinout"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "50"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation on
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "5.1"
}
Block {
BlockType Reference
Name "SinCtrl"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [185, 232, 250, 248]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "SinCtrl"
ppat "e:\\ljltx\\sinout\\DSPBuilder_singt"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;"
"sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "SinLUT"
Ports [1, 1]
Position [105, 118, 190, 162]
ForegroundColor "blue"
SourceBlock "gate_alteradspbuilder/LUT"
SourceType "LUT AlteraBlockSet"
BusType "Unsigned Integer"
bwl "8"
bwr "0"
bwaddr "10"
MatlabArray "127*sin( [0:2*pi/(2^10):2*pi] )+128"
LocPin "singtSinLUT"
lpm on
modulename "e:\\ljltx\\sinout\\DSPBuilder_singt\\singtSinLU"
"T.lut"
pipeline on
IslibDir "0"
clken off
ena off
SIGNALCOMPILER_PARAMS "BusType;Unsigned Integer;bwl;8;bwr;0;bwaddr;10;"
"lpm;on;pipeline;on;clken;off;LocPin;singtSinLUT;ena;off"
}
Block {
BlockType Reference
Name "SinOut"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [435, 147, 500, 163]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Output Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
SIGNALCOMPILER_PARAMS "sgn;Unsigned Integer;nodetype;Output Port;bwl;8"
";bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Step
Name "Step"
Position [85, 225, 115, 255]
Time "5000"
SampleTime "0"
}
Line {
SrcBlock "Incount"
SrcPort 1
DstBlock "SinLUT"
DstPort 1
}
Line {
SrcBlock "SinLUT"
SrcPort 1
DstBlock "Delay"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "SinOut"
DstPort 1
}
Line {
SrcBlock "SinOut"
SrcPort 1
DstBlock "Scope"
DstPort 1
}
Line {
SrcBlock "SinCtrl"
SrcPort 1
Points [50, 0]
Branch {
Points [195, 0; 0, -70]
DstBlock "Scope"
DstPort 2
}
Branch {
Points [0, -75]
DstBlock "Product"
DstPort 2
}
}
Line {
SrcBlock "Step"
SrcPort 1
DstBlock "SinCtrl"
DstPort 1
}
Annotation {
Name "STEP"
Position [279, 249]
}
Annotation {
Name "STEP"
Position [326, 214]
}
}
}
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