singt.tan.rpt

dds正弦可控发生计全结果 用到matlab

; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 50 ns              ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock                        ;                    ; User Pin ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                         ; To                                                                                                                                                                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 43.008 ns                               ; 143.02 MHz ( period = 6.992 ns )                    ; lpm_rom:SinLUTi|altrom:srom|altsyncram:rom_block|altsyncram_ch01:auto_generated|ram_block1a1~porta_address_reg9                                                                                              ; SDelay:Delayi|result[1]                                                                                                                                                                                      ; clock      ; clock    ; 50.000 ns                   ; 49.302 ns                 ; 6.294 ns                ;
; 43.008 ns                               ; 143.02 MHz ( period = 6.992 ns )                    ; lpm_rom:SinLUTi|altrom:srom|altsyncram:rom_block|altsyncram_ch01:auto_generated|ram_block1a1~porta_address_reg8                                                                                              ; SDelay:Delayi|result[1]                                                                                                                                                                                      ; clock      ; clock    ; 50.000 ns                   ; 49.302 ns                 ; 6.294 ns                ;
; 43.008 ns                               ; 143.02 MHz ( period = 6.992 ns )                    ; lpm_rom:SinLUTi|altrom:srom|altsyncram:rom_block|altsyncram_ch01:auto_generated|ram_block1a1~porta_address_reg7                                                                                              ; SDelay:Delayi|result[1]                                                                                                                                                                                      ; clock      ; clock    ; 50.000 ns                   ; 49.302 ns                 ; 6.294 ns                ;
; 43.008 ns                               ; 143.02 MHz ( period = 6.992 ns )                    ; lpm_rom:SinLUTi|altrom:srom|altsyncram:rom_block|altsyncram_ch01:auto_generated|ram_block1a1~porta_address_reg6                                                                                              ; SDelay:Delayi|result[1]                                                                                                                                                                                      ; clock      ; clock    ; 50.000 ns                   ; 49.302 ns                 ; 6.294 ns                ;
; 43.008 ns                               ; 143.02 MHz ( period = 6.992 ns )                    ; lpm_rom:SinLUTi|altrom:srom|altsyncram:rom_block|altsyncram_ch01:auto_generated|ram_block1a1~porta_address_reg5                                                                                              ; SDelay:Delayi|result[1]                                                                                                                                                                                      ; clock      ; clock    ; 50.000 ns                   ; 49.302 ns                 ; 6.294 ns                ;
; 43.008 ns                               ; 143.02 MHz ( period = 6.992 ns )                    ; lpm_rom:SinLUTi|altrom:srom|altsyncram:rom_block|altsyncram_ch01:auto_generated|ram_block1a1~porta_address_reg4                                                                                              ; SDelay:Delayi|result[1]                                                                                                                                                                                      ; clock      ; clock    ; 50.000 ns                   ; 49.302 ns                 ; 6.294 ns                ;