singt.tan.rpt

dds正弦可控发生计全结果 用到matlab

without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+---------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                                                                                               ; To                                                                                                                                                                                         ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A       ; None                             ; 10.109 ns                        ; SinCtrl                                                                                                                                                                                                                                            ; sld_signaltap:singt|acq_trigger_in_reg[7]                                                                                                                                                  ; --                           ; clock                        ; 0            ;
; Worst-case tco                              ; N/A       ; None                             ; 13.744 ns                        ; SDelay:Delayi|result[0]                                                                                                                                                                                                                            ; SinOut[5]                                                                                                                                                                                  ; clock                        ; --                           ; 0            ;
; Worst-case tpd                              ; N/A       ; None                             ; 18.629 ns                        ; SinCtrl                                                                                                                                                                                                                                            ; SinOut[5]                                                                                                                                                                                  ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A       ; None                             ; 2.540 ns                         ; altera_internal_jtag                                                                                                                                                                                                                               ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]                                                                                                                                                ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; 21.121 ns ; 20.00 MHz ( period = 50.000 ns ) ; 128.90 MHz ( period = 7.758 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]                                                                                                                                                                                                 ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                                               ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clock'                        ; 43.008 ns ; 20.00 MHz ( period = 50.000 ns ) ; 143.02 MHz ( period = 6.992 ns ) ; lpm_rom:SinLUTi|altrom:srom|altsyncram:rom_block|altsyncram_ch01:auto_generated|ram_block1a1~porta_address_reg9                                                                                                                                    ; SDelay:Delayi|result[1]                                                                                                                                                                    ; clock                        ; clock                        ; 0            ;
; Clock Hold: 'clock'                         ; 0.861 ns  ; 20.00 MHz ( period = 50.000 ns ) ; N/A                              ; sld_signaltap:singt|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|holdff ; sld_signaltap:singt|acq_data_in_pipe_reg[2][6]                                                                                                                                             ; clock                        ; clock                        ; 0            ;
; Clock Hold: 'altera_internal_jtag~TCKUTAP'  ; 0.867 ns  ; 20.00 MHz ( period = 50.000 ns ) ; N/A                              ; sld_signaltap:singt|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[12]                                                         ; sld_signaltap:singt|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[11] ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Total number of failed paths                ;           ;                                  ;                                  ;                                                                                                                                                                                                                                                    ;                                                                                                                                                                                            ;                              ;                              ; 0            ;
+---------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;