mpc5200

UrJTAG package is free software, covered by the GNU General Public License, and you are welcome to

#
# $Id$
#
# Copyright (C) 2002 ETC s.r.o.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# as published by the Free Software Foundation; either version 2
# of the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
# 02111-1307, USA.
#
# Written by Asier Llano <[e-mail]>, 2004.
#
# Documentation:
# [1] Freescale, "Freescale MPC5200 Users Guide", Rev. 2, 08/2004
#     Order Number: MPC5200UG
# [2] Freescale, "MPC5200BSDL", Rev. 1.2,
#     Order Number: MPC5200BSDL
#

# see Table 2-1 in [1]
signal TEST_MODE_0 B02
signal TEST_MODE_1 A01
signal TEST_SEL_0 B01
signal TEST_SEL_1 C03
signal RTC_XTAL_IN C02
signal RTC_XTAL_OUT C01
signal TIMER_2 D03
signal TIMER_3 D02
signal TIMER_4 D01
signal TIMER_5 E03
signal TIMER_6 E02
signal TIMER_7 E01
signal USB_9 F03
signal USB_8 F02
signal USB_7 F01
signal USB_6 G04
signal USB_5 G03
signal USB_4 G02
signal USB_3 G01
signal USB_2 H03
signal USB_1 H02
signal USB_0 H01
signal ETH_17 J04
signal ETH_10 J03
signal ETH_4 J02
signal ETH_3 J01
signal ETH_2 K03
signal ETH_1 K02
signal ETH_0 K01
signal ETH_11 L04
signal ETH_5 L03
signal ETH_16 L02
signal ETH_9 L01
signal ETH_8 M03
signal ETH_12 M02
signal ETH_13 M01
signal ETH_14 N04
signal ETH_15 N03
signal ETH_6 N02
signal ETH_7 N01
signal IRQ0 P03
signal IRQ2 P02
signal IRQ1 P01
signal PCI_GNT_B R04
signal EXT_AD_30 R03
signal PCI_RESET_B R02
signal IRQ3 R01
signal EXT_AD_28 T03
signal EXT_AD_26 T02
signal PCI_CLOCK T01
signal EXT_AD_24 U03
signal PCI_IDSEL U02
signal PCI_REQ_B U01
signal EXT_AD_20 V02
signal EXT_AD_31 V01
signal EXT_AD_29 W01
signal EXT_AD_27 Y01
signal EXT_AD_25 W02
signal PCI_CBE_3_B Y02
signal EXT_AD_22 V03
signal EXT_AD_23 W03
signal EXT_AD_21 Y03
signal EXT_AD_18 V04
signal EXT_AD_16 W04
signal EXT_AD_19 Y04
signal PCI_FRAME_B V05
signal PCI_TRDY_B W05
signal EXT_AD_17 Y05
signal PCI_STOP_B V06
signal PCI_CBE_2_B W06
signal PCI_IRDY_B Y06
signal PCI_PAR V07
signal PCI_DEVSEL_B W07
signal PCI_PERR_B Y07
signal EXT_AD_15 U08
signal EXT_AD_13 V08
signal PCI_SERR_B W08
signal PCI_CBE_1_B Y08
signal EXT_AD_11 V09
signal EXT_AD_14 W09
signal EXT_AD_12 Y09
signal EXT_AD_9 V10
signal PCI_CBE_0_B W10
signal EXT_AD_10 Y10
signal EXT_AD_6 U11
signal EXT_AD_4 V11
signal EXT_AD_8 W11
signal EXT_AD_7 Y11
signal EXT_AD_2 V12
signal EXT_AD_5 W12
signal EXT_AD_3 Y12
signal EXT_AD_0 V13
signal EXT_AD_1 W13
signal LP_TS_B Y13
signal LP_ACK U14
signal LP_ALE_B V14
signal LP_CS0_B W14
signal LP_CS1_B Y14
signal LP_CS2_B V15
signal LP_CS3_B W15
signal LP_CS4_B Y15
signal LP_CS5_B V16
signal LP_RW W16
signal ATA_ISOLATION Y16
signal ATA_DRQ V17
signal ATA_IOW_B W17
signal ATA_IOR_B Y17
signal ATA_IOCHRDY W18
signal ATA_DACK_B Y18
signal ATA_INTRQ Y19
signal TIMER_0 Y20
signal I2C_1 W19
signal I2C_3 W20
signal TIMER_1 V18
signal I2C_0 V19
signal I2C_2 V20
signal MEM_MDQ_31 U18
signal MEM_MDQ_1 U19
signal MEM_MDQ_0 U20
signal MEM_MDQ_30 T18
signal MEM_MDQ_3 T19
signal MEM_MDQ_2 T20
signal MEM_MDQ_28 R17
signal MEM_MDQ_29 R18
signal MEM_MDQ_5 R19
signal MEM_MDQ_4 R20
signal MEM_MDQ_27 P18
signal MEM_MDQ_7 P19
signal MEM_MDQ_6 P20
signal MEM_MDQ_25 N17
signal MEM_MDQ_26 N18
signal MEM_DQM_0 N19
signal MEM_MDQS_0 N20
signal MEM_MDQ_24 M18
signal MEM_MDQ_14 M19
signal MEM_MDQ_15 M20
signal MEM_DQM_3 L17
signal MEM_MDQS_3 L18
signal MEM_MDQ_12 L19
signal MEM_MDQ_13 L20
signal MEM_MDQ_23 K18
signal MEM_MDQ_10 K19
signal MEM_MDQ_11 K20
signal MEM_MDQ_22 J17
signal MEM_MDQ_21 J18
signal MEM_MDQ_8 J19
signal MEM_MDQ_9 J20
signal MEM_MDQ_20 H18
signal MEM_DQM_1 H19
signal MEM_MDQS_1 H20
signal MEM_MDQ_18 G17
signal MEM_MDQ_19 G18
signal MEM_CLK G19
signal MEM_CLK_B G20 G19
signal MEM_MDQ_17 F18
signal MEM_MA_12 F19
signal MEM_CLK_EN F20
signal MEM_MDQ_16 E18
signal MEM_MA_9 E19
signal MEM_MA_11 E20
signal MEM_MDQS_2 D18
signal MEM_MA_7 D19
signal MEM_MA_8 D20
signal MEM_MA_6 C20
signal MEM_MA_5 C19
signal MEM_MA_4 B20
signal MEM_DQM_2 A20
signal MEM_CAS_B B19
signal MEM_WE_B A19
signal MEM_MBA_0 C18
signal MEM_CS_0_B B18
signal MEM_RAS_B A18
signal MEM_MA_0 C17
signal MEM_MA_10 B17
signal MEM_MBA_1 A17
signal MEM_MA_3 C16
signal MEM_MA_2 B16
signal MEM_MA_1 A16
signal GPIO_WKUP_6 C15
signal SYS_PLL_TPA B15
signal SYS_XTAL_IN A15
signal SYS_XTAL_OUT D14
signal SYS_PLL_AVSS C14
signal SYS_PLL_AVDD B14
signal SRESET_B A14
signal PSC6_3 C13
signal HRESET_B B13
signal PORRESET_B A13
signal GPIO_WKUP_7 C12
signal PSC6_0 B12
signal PSC6_2 A12
signal PSC6_1 C11
signal PSC1_0 B11
signal PSC1_1 A11
signal PSC1_2 C10
signal PSC1_3 B10
signal PSC1_4 A10
signal PSC2_0 C09
signal PSC2_1 B09
signal PSC2_2 A09
signal LP_OE D08
signal CORE_PLL_AVDD C08
signal PSC2_3 B08
signal PSC2_4 A08
signal PSC3_0 C07
signal PSC3_1 B07
signal PSC3_2 A07
signal PSC3_3 C06
signal PSC3_4 B06
signal PSC3_5 A06
signal PSC3_6 C05
signal PSC3_7 B05
signal PSC3_8 A05
signal PSC3_9 C04
signal JTAG_TCK B04
signal JTAG_TMS A04
signal JTAG_TDI A03
signal JTAG_TRST_B B03
signal JTAG_TDO A02
signal VDD_MEM_IO P17 M17 T17 K17 F17 E17 H17 D17 D15 D13 D12
signal VDD_IO U16 U13 U10 U09 U06 U05 T04 F04 E04 H04 D09 D06
signal VDD_CORE U15 U12 U07 P04 K04 M04 D10 D07 D05 D11
signal VSS_IO_CORE D16


register	BSR	615
register	BR	1
register	DIR	32

instruction length 6

# see Table 21-2 in [1]

# Mandatory instructions
instruction IDCODE 011101 DIR
instruction BYPASS 111111 BR
instruction SAMPLE/PRELOAD 100000 BSR
instruction EXTEST 000000 BSR

# Optional instructions
instruction CLAMP 100001 BR
instruction HIGHZ 011111 BR


# see [2]
bit 614 I 1 PSC3_9
bit 613 O 1 PSC3_9 612 1 Z
bit 612 C 1 *
bit 611 I 1 PSC3_8
bit 610 O 1 PSC3_8 609 1 Z
bit 609 C 1 *
bit 608 I 1 PSC3_7
bit 607 O 1 PSC3_7 606 1 Z
bit 606 C 1 *
bit 605 I 1 PSC3_6
bit 604 O 1 PSC3_6 603 1 Z
bit 603 C 1 *
bit 602 I 1 PSC3_5
bit 601 O 1 PSC3_5 600 1 Z
bit 600 C 1 *
bit 599 I 1 PSC3_4
bit 598 O 1 PSC3_4 597 1 Z
bit 597 C 1 *
bit 596 I 1 PSC3_3
bit 595 O 1 PSC3_3 594 1 Z
bit 594 C 1 *
bit 593 I 1 PSC3_2
bit 592 O 1 PSC3_2 591 1 Z
bit 591 C 1 *
bit 590 I 1 PSC3_1
bit 589 O 1 PSC3_1 588 1 Z
bit 588 C 1 *
bit 587 I 1 PSC3_0
bit 586 O 1 PSC3_0 585 1 Z
bit 585 C 1 *
bit 584 I 1 PSC2_4
bit 583 O 1 PSC2_4 582 1 Z
bit 582 C 1 *
bit 581 I 1 PSC2_3
bit 580 O 1 PSC2_3 579 1 Z
bit 579 C 1 *
bit 578 I 1 LP_OE
bit 577 O 1 LP_OE 576 1 Z
bit 576 C 1 *
bit 575 I 1 PSC2_2
bit 574 O 1 PSC2_2 573 1 Z
bit 573 C 1 *
bit 572 I 1 PSC2_1
bit 571 O 1 PSC2_1 570 1 Z
bit 570 C 1 *
bit 569 I 1 PSC2_0
bit 568 O 1 PSC2_0 567 1 Z
bit 567 C 1 *
bit 566 I 1 PSC1_4
bit 565 O 1 PSC1_4 564 1 Z
bit 564 C 1 *
bit 563 I 1 PSC1_3
bit 562 O 1 PSC1_3 561 1 Z
bit 561 C 1 *
bit 560 I 1 PSC1_2
bit 559 O 1 PSC1_2 558 1 Z
bit 558 C 1 *
bit 557 I 1 PSC1_1
bit 556 O 1 PSC1_1 555 1 Z
bit 555 C 1 *
bit 554 I 1 PSC1_0
bit 553 O 1 PSC1_0 552 1 Z
bit 552 C 1 *
bit 551 I 1 PSC6_1
bit 550 O 1 PSC6_1 549 1 Z
bit 549 C 1 *
bit 548 I 1 PSC6_2
bit 547 O 1 PSC6_2 546 1 Z
bit 546 C 1 *
bit 545 I 1 PSC6_0
bit 544 O 1 PSC6_0 543 1 Z
bit 543 C 1 *
bit 542 I 1 GPIO_WKUP_7
bit 541 O 1 GPIO_WKUP_7 540 1 Z
bit 540 C 1 *
bit 539 I 1 PORRESET_B
bit 538 O 0 *
bit 537 O 0 *
bit 536 I 1 HRESET_B
bit 535 O 1 HRESET_B 534 1 Z
bit 534 C 1 *
bit 533 I 1 PSC6_3
bit 532 O 1 PSC6_3 531 1 Z
bit 531 C 1 *
bit 530 I 1 SRESET_B
bit 529 O 1 SRESET_B 528 1 Z
bit 528 C 1 *
bit 527 I 1 SYS_PLL_TPA
bit 526 O 1 SYS_PLL_TPA 525 1 Z
bit 525 C 1 *
bit 524 I 1 GPIO_WKUP_6
bit 523 O 1 GPIO_WKUP_6 522 1 Z
bit 522 C 1 *
bit 521 I 1 MEM_MA_1
bit 520 O 1 MEM_MA_1 519 1 Z
bit 519 C 1 *
bit 518 I 1 MEM_MA_2
bit 517 O 1 MEM_MA_2 516 1 Z
bit 516 C 1 *
bit 515 I 1 MEM_MA_3
bit 514 O 1 MEM_MA_3 513 1 Z
bit 513 C 1 *
bit 512 I 1 MEM_MBA_1
bit 511 O 1 MEM_MBA_1 510 1 Z
bit 510 C 1 *
bit 509 I 1 MEM_MA_10
bit 508 O 1 MEM_MA_10 507 1 Z
bit 507 C 1 *
bit 506 I 1 MEM_MA_0
bit 505 O 1 MEM_MA_0 504 1 Z
bit 504 C 1 *
bit 503 I 1 MEM_RAS_B
bit 502 O 1 MEM_RAS_B 501 1 Z
bit 501 C 1 *
bit 500 I 1 MEM_CS_0_B
bit 499 O 1 MEM_CS_0_B 498 1 Z
bit 498 C 1 *
bit 497 I 1 MEM_MBA_0
bit 496 O 1 MEM_MBA_0 495 1 Z
bit 495 C 1 *
bit 494 I 1 MEM_WE_B
bit 493 O 1 MEM_WE_B 492 1 Z
bit 492 C 1 *
bit 491 I 1 MEM_CAS_B
bit 490 O 1 MEM_CAS_B 489 1 Z
bit 489 C 1 *
bit 488 I 1 MEM_DQM_2
bit 487 O 1 MEM_DQM_2 486 1 Z
bit 486 C 1 *
bit 485 I 1 MEM_MA_4
bit 484 O 1 MEM_MA_4 483 1 Z
bit 483 C 1 *
bit 482 I 1 MEM_MA_5
bit 481 O 1 MEM_MA_5 480 1 Z
bit 480 C 1 *
bit 479 I 1 MEM_MA_6
bit 478 O 1 MEM_MA_6 477 1 Z
bit 477 C 1 *
bit 476 I 1 MEM_MA_8
bit 475 O 1 MEM_MA_8 474 1 Z
bit 474 C 1 *
bit 473 I 1 MEM_MA_7
bit 472 O 1 MEM_MA_7 471 1 Z
bit 471 C 1 *
bit 470 I 1 MEM_MDQS_2
bit 469 O 1 MEM_MDQS_2 468 1 Z
bit 468 C 1 *
bit 467 I 1 MEM_MA_11
bit 466 O 1 MEM_MA_11 465 1 Z
bit 465 C 1 *
bit 464 I 1 MEM_MA_9
bit 463 O 1 MEM_MA_9 462 1 Z
bit 462 C 1 *
bit 461 I 1 MEM_MDQ_16
bit 460 O 1 MEM_MDQ_16 459 1 Z
bit 459 C 1 *
bit 458 I 1 MEM_CLK_EN
bit 457 O 1 MEM_CLK_EN 456 1 Z
bit 456 C 1 *
bit 455 I 1 MEM_MA_12
bit 454 O 1 MEM_MA_12 453 1 Z
bit 453 C 1 *
bit 452 I 1 MEM_MDQ_17
bit 451 O 1 MEM_MDQ_17 450 1 Z
bit 450 C 1 *
bit 449 I 1 MEM_CLK_B
bit 448 O 1 MEM_CLK_B 447 1 Z
bit 447 C 1 *
bit 446 I 1 MEM_CLK
bit 445 O 1 MEM_CLK 444 1 Z
bit 444 C 1 *
bit 443 I 1 MEM_MDQ_19