gio_defs_asm.h

Axis 221 camera embedded programing interface

#define reg_gio_rw_ack_intr___intr3___width 1
#define reg_gio_rw_ack_intr___intr3___bit 3
#define reg_gio_rw_ack_intr___intr4___lsb 4
#define reg_gio_rw_ack_intr___intr4___width 1
#define reg_gio_rw_ack_intr___intr4___bit 4
#define reg_gio_rw_ack_intr___intr5___lsb 5
#define reg_gio_rw_ack_intr___intr5___width 1
#define reg_gio_rw_ack_intr___intr5___bit 5
#define reg_gio_rw_ack_intr___intr6___lsb 6
#define reg_gio_rw_ack_intr___intr6___width 1
#define reg_gio_rw_ack_intr___intr6___bit 6
#define reg_gio_rw_ack_intr___intr7___lsb 7
#define reg_gio_rw_ack_intr___intr7___width 1
#define reg_gio_rw_ack_intr___intr7___bit 7
#define reg_gio_rw_ack_intr___i2c0_done___lsb 8
#define reg_gio_rw_ack_intr___i2c0_done___width 1
#define reg_gio_rw_ack_intr___i2c0_done___bit 8
#define reg_gio_rw_ack_intr___i2c1_done___lsb 9
#define reg_gio_rw_ack_intr___i2c1_done___width 1
#define reg_gio_rw_ack_intr___i2c1_done___bit 9
#define reg_gio_rw_ack_intr_offset 132

/* Register r_intr, scope gio, type r */
#define reg_gio_r_intr___intr0___lsb 0
#define reg_gio_r_intr___intr0___width 1
#define reg_gio_r_intr___intr0___bit 0
#define reg_gio_r_intr___intr1___lsb 1
#define reg_gio_r_intr___intr1___width 1
#define reg_gio_r_intr___intr1___bit 1
#define reg_gio_r_intr___intr2___lsb 2
#define reg_gio_r_intr___intr2___width 1
#define reg_gio_r_intr___intr2___bit 2
#define reg_gio_r_intr___intr3___lsb 3
#define reg_gio_r_intr___intr3___width 1
#define reg_gio_r_intr___intr3___bit 3
#define reg_gio_r_intr___intr4___lsb 4
#define reg_gio_r_intr___intr4___width 1
#define reg_gio_r_intr___intr4___bit 4
#define reg_gio_r_intr___intr5___lsb 5
#define reg_gio_r_intr___intr5___width 1
#define reg_gio_r_intr___intr5___bit 5
#define reg_gio_r_intr___intr6___lsb 6
#define reg_gio_r_intr___intr6___width 1
#define reg_gio_r_intr___intr6___bit 6
#define reg_gio_r_intr___intr7___lsb 7
#define reg_gio_r_intr___intr7___width 1
#define reg_gio_r_intr___intr7___bit 7
#define reg_gio_r_intr___i2c0_done___lsb 8
#define reg_gio_r_intr___i2c0_done___width 1
#define reg_gio_r_intr___i2c0_done___bit 8
#define reg_gio_r_intr___i2c1_done___lsb 9
#define reg_gio_r_intr___i2c1_done___width 1
#define reg_gio_r_intr___i2c1_done___bit 9
#define reg_gio_r_intr_offset 136

/* Register r_masked_intr, scope gio, type r */
#define reg_gio_r_masked_intr___intr0___lsb 0
#define reg_gio_r_masked_intr___intr0___width 1
#define reg_gio_r_masked_intr___intr0___bit 0
#define reg_gio_r_masked_intr___intr1___lsb 1
#define reg_gio_r_masked_intr___intr1___width 1
#define reg_gio_r_masked_intr___intr1___bit 1
#define reg_gio_r_masked_intr___intr2___lsb 2
#define reg_gio_r_masked_intr___intr2___width 1
#define reg_gio_r_masked_intr___intr2___bit 2
#define reg_gio_r_masked_intr___intr3___lsb 3
#define reg_gio_r_masked_intr___intr3___width 1
#define reg_gio_r_masked_intr___intr3___bit 3
#define reg_gio_r_masked_intr___intr4___lsb 4
#define reg_gio_r_masked_intr___intr4___width 1
#define reg_gio_r_masked_intr___intr4___bit 4
#define reg_gio_r_masked_intr___intr5___lsb 5
#define reg_gio_r_masked_intr___intr5___width 1
#define reg_gio_r_masked_intr___intr5___bit 5
#define reg_gio_r_masked_intr___intr6___lsb 6
#define reg_gio_r_masked_intr___intr6___width 1
#define reg_gio_r_masked_intr___intr6___bit 6
#define reg_gio_r_masked_intr___intr7___lsb 7
#define reg_gio_r_masked_intr___intr7___width 1
#define reg_gio_r_masked_intr___intr7___bit 7
#define reg_gio_r_masked_intr___i2c0_done___lsb 8
#define reg_gio_r_masked_intr___i2c0_done___width 1
#define reg_gio_r_masked_intr___i2c0_done___bit 8
#define reg_gio_r_masked_intr___i2c1_done___lsb 9
#define reg_gio_r_masked_intr___i2c1_done___width 1
#define reg_gio_r_masked_intr___i2c1_done___bit 9
#define reg_gio_r_masked_intr_offset 140

/* Register rw_i2c0_start, scope gio, type rw */
#define reg_gio_rw_i2c0_start___run___lsb 0
#define reg_gio_rw_i2c0_start___run___width 1
#define reg_gio_rw_i2c0_start___run___bit 0
#define reg_gio_rw_i2c0_start_offset 144

/* Register rw_i2c0_cfg, scope gio, type rw */
#define reg_gio_rw_i2c0_cfg___en___lsb 0
#define reg_gio_rw_i2c0_cfg___en___width 1
#define reg_gio_rw_i2c0_cfg___en___bit 0
#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1
#define reg_gio_rw_i2c0_cfg___bit_order___width 1
#define reg_gio_rw_i2c0_cfg___bit_order___bit 1
#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2
#define reg_gio_rw_i2c0_cfg___scl_io___width 1
#define reg_gio_rw_i2c0_cfg___scl_io___bit 2
#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3
#define reg_gio_rw_i2c0_cfg___scl_inv___width 1
#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3
#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4
#define reg_gio_rw_i2c0_cfg___sda_io___width 1
#define reg_gio_rw_i2c0_cfg___sda_io___bit 4
#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5
#define reg_gio_rw_i2c0_cfg___sda_idle___width 1
#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5
#define reg_gio_rw_i2c0_cfg_offset 148

/* Register rw_i2c0_ctrl, scope gio, type rw */
#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0
#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6
#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6
#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6
#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12
#define reg_gio_rw_i2c0_ctrl___extra_start___width 3
#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15
#define reg_gio_rw_i2c0_ctrl___early_end___width 1
#define reg_gio_rw_i2c0_ctrl___early_end___bit 15
#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16
#define reg_gio_rw_i2c0_ctrl___start_stop___width 1
#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16
#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17
#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17
#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18
#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18
#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19
#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19
#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20
#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20
#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21
#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21
#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22
#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22
#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23
#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1
#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23
#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24
#define reg_gio_rw_i2c0_ctrl___start_bit___width 1
#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24
#define reg_gio_rw_i2c0_ctrl___freq___lsb 25
#define reg_gio_rw_i2c0_ctrl___freq___width 2
#define reg_gio_rw_i2c0_ctrl_offset 152

/* Register rw_i2c0_data, scope gio, type rw */
#define reg_gio_rw_i2c0_data___data0___lsb 0
#define reg_gio_rw_i2c0_data___data0___width 8
#define reg_gio_rw_i2c0_data___data1___lsb 8
#define reg_gio_rw_i2c0_data___data1___width 8
#define reg_gio_rw_i2c0_data___data2___lsb 16
#define reg_gio_rw_i2c0_data___data2___width 8
#define reg_gio_rw_i2c0_data___data3___lsb 24
#define reg_gio_rw_i2c0_data___data3___width 8
#define reg_gio_rw_i2c0_data_offset 156

/* Register rw_i2c0_data2, scope gio, type rw */
#define reg_gio_rw_i2c0_data2___data4___lsb 0
#define reg_gio_rw_i2c0_data2___data4___width 8
#define reg_gio_rw_i2c0_data2___data5___lsb 8
#define reg_gio_rw_i2c0_data2___data5___width 8
#define reg_gio_rw_i2c0_data2___start_val___lsb 16
#define reg_gio_rw_i2c0_data2___start_val___width 6
#define reg_gio_rw_i2c0_data2___ack_val___lsb 22
#define reg_gio_rw_i2c0_data2___ack_val___width 6
#define reg_gio_rw_i2c0_data2_offset 160

/* Register rw_i2c1_start, scope gio, type rw */
#define reg_gio_rw_i2c1_start___run___lsb 0
#define reg_gio_rw_i2c1_start___run___width 1
#define reg_gio_rw_i2c1_start___run___bit 0
#define reg_gio_rw_i2c1_start_offset 164

/* Register rw_i2c1_cfg, scope gio, type rw */
#define reg_gio_rw_i2c1_cfg___en___lsb 0
#define reg_gio_rw_i2c1_cfg___en___width 1
#define reg_gio_rw_i2c1_cfg___en___bit 0
#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1
#define reg_gio_rw_i2c1_cfg___bit_order___width 1
#define reg_gio_rw_i2c1_cfg___bit_order___bit 1
#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2
#define reg_gio_rw_i2c1_cfg___scl_io___width 1
#define reg_gio_rw_i2c1_cfg___scl_io___bit 2
#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3
#define reg_gio_rw_i2c1_cfg___scl_inv___width 1
#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3
#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4
#define reg_gio_rw_i2c1_cfg___sda0_io___width 1
#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4
#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5
#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5
#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6
#define reg_gio_rw_i2c1_cfg___sda1_io___width 1
#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6
#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7
#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7
#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8
#define reg_gio_rw_i2c1_cfg___sda2_io___width 1
#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8
#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9
#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9
#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10
#define reg_gio_rw_i2c1_cfg___sda3_io___width 1
#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10
#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11
#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11
#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12
#define reg_gio_rw_i2c1_cfg___sda_sel___width 2
#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14
#define reg_gio_rw_i2c1_cfg___sen_idle___width 1
#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14
#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15
#define reg_gio_rw_i2c1_cfg___sen_inv___width 1
#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15
#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16
#define reg_gio_rw_i2c1_cfg___sen_sel___width 2
#define reg_gio_rw_i2c1_cfg_offset 168

/* Register rw_i2c1_ctrl, scope gio, type rw */
#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0
#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6
#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6
#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6
#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12
#define reg_gio_rw_i2c1_ctrl___extra_start___width 3
#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15
#define reg_gio_rw_i2c1_ctrl___early_end___width 1
#define reg_gio_rw_i2c1_ctrl___early_end___bit 15
#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16
#define reg_gio_rw_i2c1_ctrl___start_stop___width 1
#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16
#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17
#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17
#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18
#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18
#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19
#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19
#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20
#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20
#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21
#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21
#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22
#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22
#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23
#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1
#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23
#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24
#define reg_gio_rw_i2c1_ctrl___start_bit___width 1
#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24
#define reg_gio_rw_i2c1_ctrl___freq___lsb 25
#define reg_gio_rw_i2c1_ctrl___freq___width 2
#define reg_gio_rw_i2c1_ctrl_offset 172

/* Register rw_i2c1_data, scope gio, type rw */
#define reg_gio_rw_i2c1_data___data0___lsb 0
#define reg_gio_rw_i2c1_data___data0___width 8
#define reg_gio_rw_i2c1_data___data1___lsb 8
#define reg_gio_rw_i2c1_data___data1___width 8
#define reg_gio_rw_i2c1_data___data2___lsb 16
#define reg_gio_rw_i2c1_data___data2___width 8
#define reg_gio_rw_i2c1_data___data3___lsb 24
#define reg_gio_rw_i2c1_data___data3___width 8
#define reg_gio_rw_i2c1_data_offset 176