gio_defs_asm.h

Axis 221 camera embedded programing interface

#ifndef __gio_defs_asm_h
#define __gio_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           gio.r
 * 
 *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

/* Register r_pa_din, scope gio, type r */
#define reg_gio_r_pa_din___data___lsb 0
#define reg_gio_r_pa_din___data___width 32
#define reg_gio_r_pa_din_offset 0

/* Register rw_pa_dout, scope gio, type rw */
#define reg_gio_rw_pa_dout___data___lsb 0
#define reg_gio_rw_pa_dout___data___width 32
#define reg_gio_rw_pa_dout_offset 4

/* Register rw_pa_oe, scope gio, type rw */
#define reg_gio_rw_pa_oe___oe___lsb 0
#define reg_gio_rw_pa_oe___oe___width 32
#define reg_gio_rw_pa_oe_offset 8

/* Register rw_pa_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte0_dout___data___lsb 0
#define reg_gio_rw_pa_byte0_dout___data___width 8
#define reg_gio_rw_pa_byte0_dout_offset 12

/* Register rw_pa_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte0_oe___oe___lsb 0
#define reg_gio_rw_pa_byte0_oe___oe___width 8
#define reg_gio_rw_pa_byte0_oe_offset 16

/* Register rw_pa_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte1_dout___data___lsb 0
#define reg_gio_rw_pa_byte1_dout___data___width 8
#define reg_gio_rw_pa_byte1_dout_offset 20

/* Register rw_pa_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte1_oe___oe___lsb 0
#define reg_gio_rw_pa_byte1_oe___oe___width 8
#define reg_gio_rw_pa_byte1_oe_offset 24

/* Register rw_pa_byte2_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte2_dout___data___lsb 0
#define reg_gio_rw_pa_byte2_dout___data___width 8
#define reg_gio_rw_pa_byte2_dout_offset 28

/* Register rw_pa_byte2_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte2_oe___oe___lsb 0
#define reg_gio_rw_pa_byte2_oe___oe___width 8
#define reg_gio_rw_pa_byte2_oe_offset 32

/* Register rw_pa_byte3_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte3_dout___data___lsb 0
#define reg_gio_rw_pa_byte3_dout___data___width 8
#define reg_gio_rw_pa_byte3_dout_offset 36

/* Register rw_pa_byte3_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte3_oe___oe___lsb 0
#define reg_gio_rw_pa_byte3_oe___oe___width 8
#define reg_gio_rw_pa_byte3_oe_offset 40

/* Register r_pb_din, scope gio, type r */
#define reg_gio_r_pb_din___data___lsb 0
#define reg_gio_r_pb_din___data___width 32
#define reg_gio_r_pb_din_offset 44

/* Register rw_pb_dout, scope gio, type rw */
#define reg_gio_rw_pb_dout___data___lsb 0
#define reg_gio_rw_pb_dout___data___width 32
#define reg_gio_rw_pb_dout_offset 48

/* Register rw_pb_oe, scope gio, type rw */
#define reg_gio_rw_pb_oe___oe___lsb 0
#define reg_gio_rw_pb_oe___oe___width 32
#define reg_gio_rw_pb_oe_offset 52

/* Register rw_pb_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte0_dout___data___lsb 0
#define reg_gio_rw_pb_byte0_dout___data___width 8
#define reg_gio_rw_pb_byte0_dout_offset 56

/* Register rw_pb_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte0_oe___oe___lsb 0
#define reg_gio_rw_pb_byte0_oe___oe___width 8
#define reg_gio_rw_pb_byte0_oe_offset 60

/* Register rw_pb_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte1_dout___data___lsb 0
#define reg_gio_rw_pb_byte1_dout___data___width 8
#define reg_gio_rw_pb_byte1_dout_offset 64

/* Register rw_pb_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte1_oe___oe___lsb 0
#define reg_gio_rw_pb_byte1_oe___oe___width 8
#define reg_gio_rw_pb_byte1_oe_offset 68

/* Register rw_pb_byte2_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte2_dout___data___lsb 0
#define reg_gio_rw_pb_byte2_dout___data___width 8
#define reg_gio_rw_pb_byte2_dout_offset 72

/* Register rw_pb_byte2_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte2_oe___oe___lsb 0
#define reg_gio_rw_pb_byte2_oe___oe___width 8
#define reg_gio_rw_pb_byte2_oe_offset 76

/* Register rw_pb_byte3_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte3_dout___data___lsb 0
#define reg_gio_rw_pb_byte3_dout___data___width 8
#define reg_gio_rw_pb_byte3_dout_offset 80

/* Register rw_pb_byte3_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte3_oe___oe___lsb 0
#define reg_gio_rw_pb_byte3_oe___oe___width 8
#define reg_gio_rw_pb_byte3_oe_offset 84

/* Register r_pc_din, scope gio, type r */
#define reg_gio_r_pc_din___data___lsb 0
#define reg_gio_r_pc_din___data___width 16
#define reg_gio_r_pc_din_offset 88

/* Register rw_pc_dout, scope gio, type rw */
#define reg_gio_rw_pc_dout___data___lsb 0
#define reg_gio_rw_pc_dout___data___width 16
#define reg_gio_rw_pc_dout_offset 92

/* Register rw_pc_oe, scope gio, type rw */
#define reg_gio_rw_pc_oe___oe___lsb 0
#define reg_gio_rw_pc_oe___oe___width 16
#define reg_gio_rw_pc_oe_offset 96

/* Register rw_pc_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pc_byte0_dout___data___lsb 0
#define reg_gio_rw_pc_byte0_dout___data___width 8
#define reg_gio_rw_pc_byte0_dout_offset 100

/* Register rw_pc_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pc_byte0_oe___oe___lsb 0
#define reg_gio_rw_pc_byte0_oe___oe___width 8
#define reg_gio_rw_pc_byte0_oe_offset 104

/* Register rw_pc_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pc_byte1_dout___data___lsb 0
#define reg_gio_rw_pc_byte1_dout___data___width 8
#define reg_gio_rw_pc_byte1_dout_offset 108

/* Register rw_pc_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pc_byte1_oe___oe___lsb 0
#define reg_gio_rw_pc_byte1_oe___oe___width 8
#define reg_gio_rw_pc_byte1_oe_offset 112

/* Register r_pd_din, scope gio, type r */
#define reg_gio_r_pd_din___data___lsb 0
#define reg_gio_r_pd_din___data___width 32
#define reg_gio_r_pd_din_offset 116

/* Register rw_intr_cfg, scope gio, type rw */
#define reg_gio_rw_intr_cfg___intr0___lsb 0
#define reg_gio_rw_intr_cfg___intr0___width 3
#define reg_gio_rw_intr_cfg___intr1___lsb 3
#define reg_gio_rw_intr_cfg___intr1___width 3
#define reg_gio_rw_intr_cfg___intr2___lsb 6
#define reg_gio_rw_intr_cfg___intr2___width 3
#define reg_gio_rw_intr_cfg___intr3___lsb 9
#define reg_gio_rw_intr_cfg___intr3___width 3
#define reg_gio_rw_intr_cfg___intr4___lsb 12
#define reg_gio_rw_intr_cfg___intr4___width 3
#define reg_gio_rw_intr_cfg___intr5___lsb 15
#define reg_gio_rw_intr_cfg___intr5___width 3
#define reg_gio_rw_intr_cfg___intr6___lsb 18
#define reg_gio_rw_intr_cfg___intr6___width 3
#define reg_gio_rw_intr_cfg___intr7___lsb 21
#define reg_gio_rw_intr_cfg___intr7___width 3
#define reg_gio_rw_intr_cfg_offset 120

/* Register rw_intr_pins, scope gio, type rw */
#define reg_gio_rw_intr_pins___intr0___lsb 0
#define reg_gio_rw_intr_pins___intr0___width 4
#define reg_gio_rw_intr_pins___intr1___lsb 4
#define reg_gio_rw_intr_pins___intr1___width 4
#define reg_gio_rw_intr_pins___intr2___lsb 8
#define reg_gio_rw_intr_pins___intr2___width 4
#define reg_gio_rw_intr_pins___intr3___lsb 12
#define reg_gio_rw_intr_pins___intr3___width 4
#define reg_gio_rw_intr_pins___intr4___lsb 16
#define reg_gio_rw_intr_pins___intr4___width 4
#define reg_gio_rw_intr_pins___intr5___lsb 20
#define reg_gio_rw_intr_pins___intr5___width 4
#define reg_gio_rw_intr_pins___intr6___lsb 24
#define reg_gio_rw_intr_pins___intr6___width 4
#define reg_gio_rw_intr_pins___intr7___lsb 28
#define reg_gio_rw_intr_pins___intr7___width 4
#define reg_gio_rw_intr_pins_offset 124

/* Register rw_intr_mask, scope gio, type rw */
#define reg_gio_rw_intr_mask___intr0___lsb 0
#define reg_gio_rw_intr_mask___intr0___width 1
#define reg_gio_rw_intr_mask___intr0___bit 0
#define reg_gio_rw_intr_mask___intr1___lsb 1
#define reg_gio_rw_intr_mask___intr1___width 1
#define reg_gio_rw_intr_mask___intr1___bit 1
#define reg_gio_rw_intr_mask___intr2___lsb 2
#define reg_gio_rw_intr_mask___intr2___width 1
#define reg_gio_rw_intr_mask___intr2___bit 2
#define reg_gio_rw_intr_mask___intr3___lsb 3
#define reg_gio_rw_intr_mask___intr3___width 1
#define reg_gio_rw_intr_mask___intr3___bit 3
#define reg_gio_rw_intr_mask___intr4___lsb 4
#define reg_gio_rw_intr_mask___intr4___width 1
#define reg_gio_rw_intr_mask___intr4___bit 4
#define reg_gio_rw_intr_mask___intr5___lsb 5
#define reg_gio_rw_intr_mask___intr5___width 1
#define reg_gio_rw_intr_mask___intr5___bit 5
#define reg_gio_rw_intr_mask___intr6___lsb 6
#define reg_gio_rw_intr_mask___intr6___width 1
#define reg_gio_rw_intr_mask___intr6___bit 6
#define reg_gio_rw_intr_mask___intr7___lsb 7
#define reg_gio_rw_intr_mask___intr7___width 1
#define reg_gio_rw_intr_mask___intr7___bit 7
#define reg_gio_rw_intr_mask___i2c0_done___lsb 8
#define reg_gio_rw_intr_mask___i2c0_done___width 1
#define reg_gio_rw_intr_mask___i2c0_done___bit 8
#define reg_gio_rw_intr_mask___i2c1_done___lsb 9
#define reg_gio_rw_intr_mask___i2c1_done___width 1
#define reg_gio_rw_intr_mask___i2c1_done___bit 9
#define reg_gio_rw_intr_mask_offset 128

/* Register rw_ack_intr, scope gio, type rw */
#define reg_gio_rw_ack_intr___intr0___lsb 0
#define reg_gio_rw_ack_intr___intr0___width 1
#define reg_gio_rw_ack_intr___intr0___bit 0
#define reg_gio_rw_ack_intr___intr1___lsb 1
#define reg_gio_rw_ack_intr___intr1___width 1
#define reg_gio_rw_ack_intr___intr1___bit 1
#define reg_gio_rw_ack_intr___intr2___lsb 2
#define reg_gio_rw_ack_intr___intr2___width 1
#define reg_gio_rw_ack_intr___intr2___bit 2
#define reg_gio_rw_ack_intr___intr3___lsb 3