iop_sw_mpu_defs.h

Axis 221 camera embedded programing interface

  unsigned int dummy3    : 3;
  unsigned int spu_intr3 : 1;
  unsigned int dummy4    : 19;
} reg_iop_sw_mpu_rw_ack_intr_grp0;
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88

/* Register r_intr_grp0, scope iop_sw_mpu, type r */
typedef struct {
  unsigned int spu_intr0      : 1;
  unsigned int trigger_grp0   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr1      : 1;
  unsigned int trigger_grp1   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int spu_intr2      : 1;
  unsigned int trigger_grp2   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr3      : 1;
  unsigned int trigger_grp3   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_r_intr_grp0;
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92

/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
typedef struct {
  unsigned int spu_intr0      : 1;
  unsigned int trigger_grp0   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr1      : 1;
  unsigned int trigger_grp1   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int spu_intr2      : 1;
  unsigned int trigger_grp2   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr3      : 1;
  unsigned int trigger_grp3   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_r_masked_intr_grp0;
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96

/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
typedef struct {
  unsigned int spu_intr4      : 1;
  unsigned int trigger_grp4   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr5      : 1;
  unsigned int trigger_grp5   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int spu_intr6      : 1;
  unsigned int trigger_grp6   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr7      : 1;
  unsigned int trigger_grp7   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_rw_intr_grp1_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100

/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
typedef struct {
  unsigned int spu_intr4 : 1;
  unsigned int dummy1    : 3;
  unsigned int spu_intr5 : 1;
  unsigned int dummy2    : 3;
  unsigned int spu_intr6 : 1;
  unsigned int dummy3    : 3;
  unsigned int spu_intr7 : 1;
  unsigned int dummy4    : 19;
} reg_iop_sw_mpu_rw_ack_intr_grp1;
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104

/* Register r_intr_grp1, scope iop_sw_mpu, type r */
typedef struct {
  unsigned int spu_intr4      : 1;
  unsigned int trigger_grp4   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr5      : 1;
  unsigned int trigger_grp5   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int spu_intr6      : 1;
  unsigned int trigger_grp6   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr7      : 1;
  unsigned int trigger_grp7   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_r_intr_grp1;
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108

/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
typedef struct {
  unsigned int spu_intr4      : 1;
  unsigned int trigger_grp4   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr5      : 1;
  unsigned int trigger_grp5   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int spu_intr6      : 1;
  unsigned int trigger_grp6   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr7      : 1;
  unsigned int trigger_grp7   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_r_masked_intr_grp1;
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112

/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
typedef struct {
  unsigned int spu_intr8      : 1;
  unsigned int trigger_grp0   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr9      : 1;
  unsigned int trigger_grp1   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int spu_intr10     : 1;
  unsigned int trigger_grp2   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr11     : 1;
  unsigned int trigger_grp3   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_rw_intr_grp2_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116

/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
typedef struct {
  unsigned int spu_intr8  : 1;
  unsigned int dummy1     : 3;
  unsigned int spu_intr9  : 1;
  unsigned int dummy2     : 3;
  unsigned int spu_intr10 : 1;
  unsigned int dummy3     : 3;
  unsigned int spu_intr11 : 1;
  unsigned int dummy4     : 19;
} reg_iop_sw_mpu_rw_ack_intr_grp2;
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120

/* Register r_intr_grp2, scope iop_sw_mpu, type r */
typedef struct {
  unsigned int spu_intr8      : 1;
  unsigned int trigger_grp0   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr9      : 1;
  unsigned int trigger_grp1   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int spu_intr10     : 1;
  unsigned int trigger_grp2   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr11     : 1;
  unsigned int trigger_grp3   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_r_intr_grp2;
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124

/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
typedef struct {
  unsigned int spu_intr8      : 1;
  unsigned int trigger_grp0   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr9      : 1;
  unsigned int trigger_grp1   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int spu_intr10     : 1;
  unsigned int trigger_grp2   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr11     : 1;
  unsigned int trigger_grp3   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_r_masked_intr_grp2;
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128

/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
typedef struct {
  unsigned int spu_intr12     : 1;
  unsigned int trigger_grp4   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr13     : 1;
  unsigned int trigger_grp5   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int spu_intr14     : 1;
  unsigned int trigger_grp6   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr15     : 1;
  unsigned int trigger_grp7   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_rw_intr_grp3_mask;
#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132

/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
typedef struct {
  unsigned int spu_intr12 : 1;
  unsigned int dummy1     : 3;
  unsigned int spu_intr13 : 1;
  unsigned int dummy2     : 3;
  unsigned int spu_intr14 : 1;
  unsigned int dummy3     : 3;
  unsigned int spu_intr15 : 1;
  unsigned int dummy4     : 19;
} reg_iop_sw_mpu_rw_ack_intr_grp3;
#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136

/* Register r_intr_grp3, scope iop_sw_mpu, type r */
typedef struct {
  unsigned int spu_intr12     : 1;
  unsigned int trigger_grp4   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr13     : 1;
  unsigned int trigger_grp5   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int spu_intr14     : 1;
  unsigned int trigger_grp6   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr15     : 1;
  unsigned int trigger_grp7   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_r_intr_grp3;
#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140

/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
typedef struct {
  unsigned int spu_intr12     : 1;
  unsigned int trigger_grp4   : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int dmc_out        : 1;
  unsigned int spu_intr13     : 1;
  unsigned int trigger_grp5   : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_in         : 1;
  unsigned int spu_intr14     : 1;
  unsigned int trigger_grp6   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int fifo_out       : 1;
  unsigned int spu_intr15     : 1;
  unsigned int trigger_grp7   : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_in        : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_mpu_r_masked_intr_grp3;
#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144


/* Constants */
enum {
  regk_iop_sw_mpu_copy                     = 0x00000000,
  regk_iop_sw_mpu_cpu                      = 0x00000000,
  regk_iop_sw_mpu_mpu                      = 0x00000001,
  regk_iop_sw_mpu_no                       = 0x00000000,
  regk_iop_sw_mpu_nop                      = 0x00000000,
  regk_iop_sw_mpu_rd                       = 0x00000002,
  regk_iop_sw_mpu_reg_copy                 = 0x00000001,
  regk_iop_sw_mpu_rw_bus_clr_mask_default  = 0x00000000,
  regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
  regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
  regk_iop_sw_mpu_rw_bus_set_mask_default  = 0x00000000,
  regk_iop_sw_mpu_rw_gio_clr_mask_default  = 0x00000000,
  regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
  regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
  regk_iop_sw_mpu_rw_gio_set_mask_default  = 0x00000000,
  regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
  regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
  regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
  regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
  regk_iop_sw_mpu_rw_sw_cfg_owner_default  = 0x00000000,
  regk_iop_sw_mpu_set                      = 0x00000001,
  regk_iop_sw_mpu_spu                      = 0x00000002,
  regk_iop_sw_mpu_wr                       = 0x00000003,
  regk_iop_sw_mpu_yes                      = 0x00000001
};
#endif /* __iop_sw_mpu_defs_h */