📄 iop_sw_cfg_defs.h
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unsigned int gio11_oe : 1; unsigned int dummy1 : 16;} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int gio12 : 3; unsigned int gio12_oe : 1; unsigned int gio13 : 3; unsigned int gio13_oe : 1; unsigned int gio14 : 3; unsigned int gio14_oe : 1; unsigned int gio15 : 3; unsigned int gio15_oe : 1; unsigned int dummy1 : 16;} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int gio16 : 3; unsigned int gio16_oe : 1; unsigned int gio17 : 3; unsigned int gio17_oe : 1; unsigned int gio18 : 3; unsigned int gio18_oe : 1; unsigned int gio19 : 3; unsigned int gio19_oe : 1; unsigned int dummy1 : 16;} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int gio20 : 3; unsigned int gio20_oe : 1; unsigned int gio21 : 3; unsigned int gio21_oe : 1; unsigned int gio22 : 3; unsigned int gio22_oe : 1; unsigned int gio23 : 3; unsigned int gio23_oe : 1; unsigned int dummy1 : 16;} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int gio24 : 3; unsigned int gio24_oe : 1; unsigned int gio25 : 3; unsigned int gio25_oe : 1; unsigned int gio26 : 3; unsigned int gio26_oe : 1; unsigned int gio27 : 3; unsigned int gio27_oe : 1; unsigned int dummy1 : 16;} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int gio28 : 3; unsigned int gio28_oe : 1; unsigned int gio29 : 3; unsigned int gio29_oe : 1; unsigned int gio30 : 3; unsigned int gio30_oe : 1; unsigned int gio31 : 3; unsigned int gio31_oe : 1; unsigned int dummy1 : 16;} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int bus0_in : 1; unsigned int bus1_in : 1; unsigned int dummy1 : 30;} reg_iop_sw_cfg_rw_spu_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int ext_clk : 3; unsigned int tmr0_en : 2; unsigned int tmr1_en : 2; unsigned int tmr2_en : 2; unsigned int tmr3_en : 2; unsigned int tmr0_dis : 2; unsigned int tmr1_dis : 2; unsigned int tmr2_dis : 2; unsigned int tmr3_dis : 2; unsigned int dummy1 : 13;} reg_iop_sw_cfg_rw_timer_grp0_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int ext_clk : 3; unsigned int tmr0_en : 2; unsigned int tmr1_en : 2; unsigned int tmr2_en : 2; unsigned int tmr3_en : 2; unsigned int tmr0_dis : 2; unsigned int tmr1_dis : 2; unsigned int tmr2_dis : 2; unsigned int tmr3_dis : 2; unsigned int dummy1 : 13;} reg_iop_sw_cfg_rw_timer_grp1_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int grp0_dis : 1; unsigned int grp0_en : 1; unsigned int grp1_dis : 1; unsigned int grp1_en : 1; unsigned int grp2_dis : 1; unsigned int grp2_en : 1; unsigned int grp3_dis : 1; unsigned int grp3_en : 1; unsigned int grp4_dis : 1; unsigned int grp4_en : 1; unsigned int grp5_dis : 1; unsigned int grp5_en : 1; unsigned int grp6_dis : 1; unsigned int grp6_en : 1; unsigned int grp7_dis : 1; unsigned int grp7_en : 1; unsigned int dummy1 : 16;} reg_iop_sw_cfg_rw_trigger_grps_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int out_strb : 4; unsigned int in_src : 2; unsigned int in_size : 3; unsigned int in_last : 2; unsigned int in_strb : 4; unsigned int dummy1 : 17;} reg_iop_sw_cfg_rw_pdp_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */typedef struct { unsigned int sdp_out_strb : 3; unsigned int sdp_in_data : 3; unsigned int sdp_in_last : 2; unsigned int sdp_in_strb : 3; unsigned int dummy1 : 21;} reg_iop_sw_cfg_rw_sdp_cfg;#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164/* Constants */enum { regk_iop_sw_cfg_a = 0x00000001, regk_iop_sw_cfg_b = 0x00000002, regk_iop_sw_cfg_bus = 0x00000000, regk_iop_sw_cfg_bus_rot16 = 0x00000002, regk_iop_sw_cfg_bus_rot24 = 0x00000003, regk_iop_sw_cfg_bus_rot8 = 0x00000001, regk_iop_sw_cfg_clk12 = 0x00000000, regk_iop_sw_cfg_cpu = 0x00000000, regk_iop_sw_cfg_gated_clk0 = 0x0000000e, regk_iop_sw_cfg_gated_clk1 = 0x0000000f, regk_iop_sw_cfg_gio0 = 0x00000004, regk_iop_sw_cfg_gio1 = 0x00000001, regk_iop_sw_cfg_gio2 = 0x00000005, regk_iop_sw_cfg_gio3 = 0x00000002, regk_iop_sw_cfg_gio4 = 0x00000006, regk_iop_sw_cfg_gio5 = 0x00000003, regk_iop_sw_cfg_gio6 = 0x00000007, regk_iop_sw_cfg_gio7 = 0x00000004, regk_iop_sw_cfg_gio_in18 = 0x00000002, regk_iop_sw_cfg_gio_in19 = 0x00000003, regk_iop_sw_cfg_gio_in20 = 0x00000004, regk_iop_sw_cfg_gio_in21 = 0x00000005, regk_iop_sw_cfg_gio_in26 = 0x00000006, regk_iop_sw_cfg_gio_in27 = 0x00000007, regk_iop_sw_cfg_gio_in4 = 0x00000000, regk_iop_sw_cfg_gio_in5 = 0x00000001, regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, regk_iop_sw_cfg_mpu = 0x00000001, regk_iop_sw_cfg_none = 0x00000000, regk_iop_sw_cfg_pdp_out = 0x00000001, regk_iop_sw_cfg_pdp_out_hi = 0x00000001, regk_iop_sw_cfg_pdp_out_lo = 0x00000000, regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, regk_iop_sw_cfg_sdp_out = 0x00000004, regk_iop_sw_cfg_size16 = 0x00000002, regk_iop_sw_cfg_size24 = 0x00000003, regk_iop_sw_cfg_size32 = 0x00000004, regk_iop_sw_cfg_size8 = 0x00000001, regk_iop_sw_cfg_spu = 0x00000002, regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, regk_iop_sw_cfg_spu_g0 = 0x00000007, regk_iop_sw_cfg_spu_g1 = 0x00000007, regk_iop_sw_cfg_spu_g2 = 0x00000007, regk_iop_sw_cfg_spu_g3 = 0x00000007, regk_iop_sw_cfg_spu_g4 = 0x00000007, regk_iop_sw_cfg_spu_g5 = 0x00000007, regk_iop_sw_cfg_spu_g6 = 0x00000007, regk_iop_sw_cfg_spu_g7 = 0x00000007, regk_iop_sw_cfg_spu_gio0 = 0x00000000, regk_iop_sw_cfg_spu_gio1 = 0x00000001, regk_iop_sw_cfg_spu_gio5 = 0x00000005, regk_iop_sw_cfg_spu_gio6 = 0x00000006, regk_iop_sw_cfg_spu_gio7 = 0x00000007, regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, regk_iop_sw_cfg_spu_gioout0 = 0x00000000, regk_iop_sw_cfg_spu_gioout1 = 0x00000000, regk_iop_sw_cfg_spu_gioout10 = 0x00000007, regk_iop_sw_cfg_spu_gioout11 = 0x00000007, regk_iop_sw_cfg_spu_gioout12 = 0x00000007, regk_iop_sw_cfg_spu_gioout13 = 0x00000007, regk_iop_sw_cfg_spu_gioout14 = 0x00000007, regk_iop_sw_cfg_spu_gioout15 = 0x00000007, regk_iop_sw_cfg_spu_gioout16 = 0x00000007, regk_iop_sw_cfg_spu_gioout17 = 0x00000007, regk_iop_sw_cfg_spu_gioout18 = 0x00000007, regk_iop_sw_cfg_spu_gioout19 = 0x00000007, regk_iop_sw_cfg_spu_gioout2 = 0x00000001, regk_iop_sw_cfg_spu_gioout20 = 0x00000007, regk_iop_sw_cfg_spu_gioout21 = 0x00000007, regk_iop_sw_cfg_spu_gioout22 = 0x00000007, regk_iop_sw_cfg_spu_gioout23 = 0x00000007, regk_iop_sw_cfg_spu_gioout24 = 0x00000007, regk_iop_sw_cfg_spu_gioout25 = 0x00000007, regk_iop_sw_cfg_spu_gioout26 = 0x00000007, regk_iop_sw_cfg_spu_gioout27 = 0x00000007, regk_iop_sw_cfg_spu_gioout28 = 0x00000007, regk_iop_sw_cfg_spu_gioout29 = 0x00000007, regk_iop_sw_cfg_spu_gioout3 = 0x00000001, regk_iop_sw_cfg_spu_gioout30 = 0x00000007, regk_iop_sw_cfg_spu_gioout31 = 0x00000007, regk_iop_sw_cfg_spu_gioout4 = 0x00000002, regk_iop_sw_cfg_spu_gioout5 = 0x00000002, regk_iop_sw_cfg_spu_gioout6 = 0x00000003, regk_iop_sw_cfg_spu_gioout7 = 0x00000003, regk_iop_sw_cfg_spu_gioout8 = 0x00000007, regk_iop_sw_cfg_spu_gioout9 = 0x00000007, regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, regk_iop_sw_cfg_timer_grp0 = 0x00000000, regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, regk_iop_sw_cfg_timer_grp1 = 0x00000000, regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, regk_iop_sw_cfg_trig0_0 = 0x00000000, regk_iop_sw_cfg_trig0_1 = 0x00000000, regk_iop_sw_cfg_trig0_2 = 0x00000000, regk_iop_sw_cfg_trig0_3 = 0x00000000, regk_iop_sw_cfg_trig1_0 = 0x00000000, regk_iop_sw_cfg_trig1_1 = 0x00000000, regk_iop_sw_cfg_trig1_2 = 0x00000000, regk_iop_sw_cfg_trig1_3 = 0x00000000, regk_iop_sw_cfg_trig2_0 = 0x00000001, regk_iop_sw_cfg_trig2_1 = 0x00000001, regk_iop_sw_cfg_trig2_2 = 0x00000001, regk_iop_sw_cfg_trig2_3 = 0x00000001, regk_iop_sw_cfg_trig3_0 = 0x00000001, regk_iop_sw_cfg_trig3_1 = 0x00000001, regk_iop_sw_cfg_trig3_2 = 0x00000001, regk_iop_sw_cfg_trig3_3 = 0x00000001, regk_iop_sw_cfg_trig4_0 = 0x00000002, regk_iop_sw_cfg_trig4_1 = 0x00000002, regk_iop_sw_cfg_trig4_2 = 0x00000002, regk_iop_sw_cfg_trig4_3 = 0x00000002, regk_iop_sw_cfg_trig5_0 = 0x00000002, regk_iop_sw_cfg_trig5_1 = 0x00000002, regk_iop_sw_cfg_trig5_2 = 0x00000002, regk_iop_sw_cfg_trig5_3 = 0x00000002, regk_iop_sw_cfg_trig6_0 = 0x00000003, regk_iop_sw_cfg_trig6_1 = 0x00000003, regk_iop_sw_cfg_trig6_2 = 0x00000003, regk_iop_sw_cfg_trig6_3 = 0x00000003, regk_iop_sw_cfg_trig7_0 = 0x00000003, regk_iop_sw_cfg_trig7_1 = 0x00000003, regk_iop_sw_cfg_trig7_2 = 0x00000003, regk_iop_sw_cfg_trig7_3 = 0x00000003};#endif /* __iop_sw_cfg_defs_h */⌨️ 快捷键说明
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